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| 型號： | TVP5146M2IPFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | GREEN, PLASTIC, HTQFP-80 |
| 文件頁數(shù)： | 85/107頁 |
| 文件大?。?/td> | 949K |
| 代理商： | TVP5146M2IPFP |
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SLES141G
– JULY 2005 – REVISED APRIL 2011
Table 2-100. VDP Full Field Enable Register
Subaddress
D9h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Full field enable
Full field enable:
0 = Disabled full field mode(default)
1 = Enabled full field mode
This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines in the line mode register
programmed with FFh are sliced with the definition of the VDP full field mode register at subaddress DAh. Values other than FFh in the
line mode registers allow a different slice mode for that particular line.
Table 2-101. VDP Full Field Mode Register
Subaddress
DAh
Default
FFh
7
6
5
4
3
2
1
0
Full field mode [7:0]
Full field mode [7:0]:
This register programs the specific VBI standard for full field mode. It can be any VBI standard. Individual line settings take priority over
the full field register. This allows each VBI line to be programmed independently but have the remaining lines in full field mode. The full
field mode register has the same bit definition as line mode registers (default FFh).
Global line mode has priority over the full field mode.
Table 2-102. VBUS Data Access With No VBUS Address Increment Register
Subaddress
E0h
Default
00h
7
6
5
4
3
2
1
0
VBUS data [7:0]
VBUS data [7:0]:
VBUS data register for VBUS single byte read/write transaction.
Table 2-103. VBUS Data Access With VBUS Address Increment Register
Subaddress
E1h
Default
00h
7
6
5
4
3
2
1
0
VBUS data [7:0]
VBUS data [7:0]:
VBUS data register for VBUS multi-byte read/write transaction. VBUS address is auto-incremented after each data byte read/write.
Table 2-104. FIFO Read Data Register
Subaddress
E2h
Read only
7
6
5
4
3
2
1
0
FIFO Read Data [7:0]
FIFO Read Data [7:0]:
This register is provided to access VBI FIFO data through the host port. All forms of teletext data come directly from the FIFO, while all
other forms of VBI data can be programmed to come from registers or from the FIFO. If the host port is to be used to read data from
the FIFO, bit 0 (host access enable) in the VDP FIFO output control register at subaddress C0h must be set to 1 (see Table 2-94).
Copyright
2005–2011, Texas Instruments Incorporated
Functional Description
79
Product Folder Link(s): TVP5146M2
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| TVP5146M2IPFPR | 功能描述:視頻 IC 10B Hi Qual Sgl-Chip Dig Video Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5146M2PFP | 功能描述:視頻 IC 10B Hi Qual Sgl-Chip Dig Vid Dec RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5146M2PFP_0708 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL/SECAM 4X10-Bit Digital Video Decoder With Macrovision Detection, YPbPr/RGB Inputs, 5-Line Comb Filter, and SCART Support |
| TVP5146M2PFPG4 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL/SECAM 4X10-Bit Digital Video Decoder With Macrovision Detection, YPbPr/RGB Inputs, 5-Line Comb Filter, and SCART Support |
| TVP5146M2PFPR | 功能描述:視頻 IC 10B Hi Qual Sgl-Chip Dig Vid Dec RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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