2–23
2n+2 SCLK’s
Start of Active Line
SCLK
PCLK
PREF
Y(0–7)
U0
Y0
V0
Y1
U2
Y2
V2
Y3
U4
Y4
Yn-4
Un-3
Yn-3 Vn-3
Yn-2 Un-1
Yn-1
Vn-1
Yn
End of Active Line
Figure 2–18. 8-Bit (uYvYuYvY) 656 Functional Timing
2.10 Reset
A two-stage reset sequence is initiated at power up or any time the RSTIB pin is brought low. In the first stage
all output pins are in high-impedance state, I/O pins are in input mode, and the RSETB pin is low. For a power
up reset the device remains in the first stge until an internal low-voltage detect goes away. For a reset
inititated by the RSTIB pin the device remains in the first stage until the RSTIB pin goes high. Table 2–7
describes the states of the I/O pins during and after the reset sequence.
Table 2–7. Power-Up Reset Sequence
SIGNAL NAMES
FIRST STAGE
SECOND STAGE
POWER-UP RESET
COMPLETED
Duration
128 SCLK
Y[7:0], UV[7:0], HSYN, VSYN, HBLC, HSIN, AVID
High-impedance
LCLk, SCLK, PCLK, PREF, PALI, GLCO
High-impedance
Active
RSTIB, SDA, SCL, I2CA, OEB, GPCL
Input
RSETB
Low
High
2.11 Internal Control Registers
A set of internal registers initializes and controls the TVP5010. These registers set all the device operating
parameters. Communication between the external controller and TVP5010 is through a standard I2C
interface port. Table 2–8 shows the summary of these registers. The reserved bits must be written with 0.
The detailed programming information of each register is described in the following sections.
Table 2–8. Registers Summary
REGISTER FUNCTION
I2C
R/W
Video input source selection
00h
W
Analog channel controls
01h
W
Operation mode controls
02h
W
Miscellaneous controls
03h
W
Reserved
04 – 5h
W
Color killer threshold control
06h
W
Luminance processing controls–#1
07h
W
Luminance processing controls–#2
08h
W
Brightness control
09h
W
Color saturation control
0Ah
W
Color hue control
0Bh
W