- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385951 > TVP3020-175 (Texas Instruments, Inc.) Video Interface PALETTE(視頻接口調(diào)色器) PDF資料下載
參數(shù)資料
| 型號： | TVP3020-175 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（視頻接口調(diào)色器） |
| 文件頁數(shù)： | 50/98頁 |
| 文件大?。?/td> | 582K |
| 代理商： | TVP3020-175 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁
2–36
2.14 Video Control: Horizontal Sync, Vertical Sync, and Blank
For the high-resolution system modes, SYSHS and SYSVS are active-low pulses that are passed through
true/complement gates to the HSYNCOUT and VSYNCOUT outputs. The output polarities of HSYNCOUT
and VSYNCOUT can be programmed through the general-control register. However, for the VGA mode, the
polarities required by the monitor are already provided at the feature connector where VGAHS and VGAVS
are sourced. Therefore, the palette passes them through to HSYNCOUT and VSYNCOUT without polarity
change. As described in Section 2.3 and Figures 2–2 through 2–5, the SYSBL, SYSHS and SYSVS inputs
are sampled and latched at the falling edge of VCLK in the system modes while VGABL, VGAVS, and
VGAHS are latched at the rising edge of CLK0 in the VGA mode. After SYSBL is sampled with VCLK, it is
sampled on the rising edge of the internal RCLK and passed to the dot clock pipeline delay. When
multiplex-control register 2 bit 7 is set to logic 1 to activate the VGA port, the CLK0, VGAHS, VGAVS, and
VGABL inputs are selected. Otherwise, VCLK, SYSHS, SYSVS, and SYSBL are selected.
HSYNC, VSYNC, and BLANK (generated either from the system mode or VGA-mode video control signals)
have internal pipeline delays so that the SYNC and BLANK signals align with the RGB data at the DAC
outputs. Due to the sample and latch timing delay, it is possible to have active SCLKs after the selected blank
input becomes active. The relationship between VCLK and SCLK and the internal VCLK sample and latch
delay needs to be carefully reviewed and programmed. See Section 2.3 and Figures 2–2 and 2–3 for more
details.
As shown in Figure 2–13, active HSYNC and VSYNC turns off the sync current source (after pipeline delay).
They are not qualified by the BLANK signal. Therefore, to ensure proper operation, HSYNC and VSYNC
should be designed such that they are active only during the blank active time.
To alter the polarity of the HSYNCOUT and VSYNCOUT outputs, the MPU must set or clear the
corresponding bits in general-control register (see Section 2.16.1). The polarity of these signals can only
be altered when not in VGA mode. These bits default to logic 0, which is an active-low output.
2.15 Split Shift-Register-Transfer VRAMs
The Viewpoint palette has direct support for split shift-register-transfer (SSRT) VRAMs. In order to allow the
VRAMs to perform a split register transfer, an extra SCLK cycle must be inserted during the blank sequence.
This is initiated when the SSRT enable bit (bit 2) in the general-control register is set to logic 1 and a rising
edge on the SFLAG input is detected. An SCLK pulse is generated within 20 ns of the rising edge of the
SFLAG signal. A minimum 15-ns logic-high duration is provided to satisfy all the –15 VRAM timing
requirements. The rising edge of the SFLAG input triggers SCLK, but it needs to stay high for a specified
minimum duration. By controlling the SFLAG timing, the delay time from the rising edge of VRAM TRG signal
to SCLK can be satisfied. The relationship between SCLK, the SFLAG input, and SYSBL is shown as
follows:
SYSBL
SSRT Enable
(general-control
register bit 2)
SFLAG Input
SCLK
Figure 2–16. Split Shift-Register-Transfer Timing
If external SFLAG logic is designed as an R–S latch that is set by split shift-register-transfer timing and reset
by SYSBL going high, the delay from SYSBL high to SFLAG low cannot exceed one half of one SCLK cycle.
Otherwise, the SCLK generation logic could fail.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3020-135 | Video Interface PALETTE(視頻接口調(diào)色器) |
| TVP3025-135 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3025-175 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3030-175 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3030-220 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3020-175MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020-200MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3020-200PCE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3020-220MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
發(fā)布緊急采購，3分鐘左右您將得到回復。