參數(shù)資料
型號: TVP3010C
廠商: Texas Instruments, Inc.
英文描述: Video Interface Palette
中文描述: 視頻接口面板
文件頁數(shù): 72/90頁
文件大?。?/td> 491K
代理商: TVP3010C
3–5
3.6 Operating Characteristics (TVP3010M)
PARAMETER
TEST CONDITIONS (see Note 4)
8/6 high
MIN
TYP
MAX
UNIT
Resolution (each DAC)
8
bits
8/6 low
6
EL
End-point linearity error
(each DAC)
8/6 high
1
LSB
8/6 low
1/4
ED
Differential linearity error
(each DAC)
8/6 high
1
LSB
8/6 low
1/4
Gray scale error
5%
White level relative to Blank
17.69
19.05
20.4
mA
White level relative to Blank
(7.5 IRE only)
16.74
17.62
18.5
mA
Output current (see Note 4)
Black level relative to Blank
(7.5 IRE only)
0.95
1.44
1.9
mA
Blank level on IOR, IOB
0
5
50
μ
A
mA
μ
A
μ
A
μ
A
Blank level on IOG (with Sync enabled)
6.29
7.6
8.96
Sync level on IOG (with Sync enabled)
0
5
50
One LSB (8/6 high)
69.1
One LSB (8/6 low)
276.4
DAC-to-DAC matching
2%
5%
DAC-to-DAC crosstalk
–20
dB
Output compliance
–0.4
1.2
V
Voltage reference output
voltage
1.1
1.235
1.3
V
Output impedance
50
k
pF
Output capacitance
f = 1 MHz,
IOUT = 0
13
Sense voltage reference
350
mV
Clock and data feedthrough
–20
dB
Glitch impulse (see Note 5)
50
pV–s
Pipeline delay VGA port
Pipeline delay, VGA port
Self-clocked timing
18 dot clock
periods
Externally clocked timing
15 dot clock
periods
Pipeline delay pixel port
Pipeline delay, pixel port
Self-clocked timing
Externally clocked timing
2 RCLK + 14 dot clock
1 RCLK +14 dot clock
periods
periods
NOTES:
4. Test conditions for RS343-A video signals (unless otherwise noted) can be found in Recommended
Operating Conditions using external voltage reference Vref = 1.235 V, RSET = 523
. When using the
internal voltage reference, RSET may need to be adjusted in order to meet these limits.
5. Glitch impulse does not include clock and data feedthrough. The – 3-dB test bandwidth is twice the clock
rate.
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