參數(shù)資料
型號(hào)： TVP3010C
廠商： Texas Instruments, Inc.
英文描述： Video Interface Palette
中文描述： 視頻接口面板
文件頁(yè)數(shù)： 13/90頁(yè)
文件大?。?/td> 491K
代理商： TVP3010C
1–7
1.4
Ordering Information
TVP3010
XXX – X – XX
Pixel Clock Frequency Indicator
Must contain three letters:
–85:
–110:
–135:
–170:
85-MHz pixel clock
110-MHz pixel clock
135-MHz pixel cock
170-MHz pixel clock
Military Extension M
Commercial Extension C
Package
Must contain two Letters:
FN: square plastic J-leaded chip carrier
GA: 84-pin (12 x 12) ceramic pin-grid array
1.5
Terminal Functions (TVP3010C and TVP3010M)
TERMINAL
I/O
DESCRIPTION
NAME
AVDD
CLK0
NO. (FN)
55, 57
NO. (GA)
J1, L11, G12
Analog power. All AVDD terminals must be connected.
Dot clock 0 input. CLK0 can be selected to drive the dot
clock at frequencies up to 140 MHz. When VGA mode is
active, the default clock source is CLK0. The maximum
frequency in VGA mode is 85 MHz.
77
K2
I
(TTL
compatible)
CLK1, CLK2
75, 76
L2, K3
I
(TTL/ECL
compatible)
Dual-mode dot clock input. These inputs are essentially
ECL-compatible inputs, but two TTL clocks may be used
on the CLK1 and CLK2 if so selected in the input clock
select register. These inputs may be selected as the dot
clock up to the device limit while in the ECL mode or up to
140 MHz in the TTL mode.
CLK3[RCLK]
74
M1
I/O
Dot clock 3 TTL input or reference clock output. When
configured as CLK3, this terminal is similar to CLK0 and
can be selected to drive the dot clock at frequencies up to
140 MHz. When configured as RCLK, this terminal outputs
the reference clock signal, which is similar to the SCLK
signal but not gated off during blanking. This signal can be
used for pixel-port timing reference or other system
synchronization. The terminal defaults to CLK3 after reset.
CLK3[LCLK]
73
L3
I
Dot clock 4 TTL input or pixel-port latch clock. CLK3[LCLK]
can be configured to drive dot clock frequencies up to 140
MHz, or it can be configured as a latch-clock input to latch
pixel-port input data. It defaults to CLK4 after reset, and
LCLK is internally connected to RCLK to latch pixel-port
data.
COMP
52
K11
I
Compensation. COMP provides compensation for the
internal reference amplifier. A 0.1-
μ
F ceramic capacitor is
required between COMP and AVDD. The COMP capacitor
must be as close to the device as possible to avoid noise
pick up.
NOTE 1:
All unused inputs should be tied to a logic level and not be allowed to float.
相關(guān)PDF資料
PDF描述
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TVP3010M 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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