參數(shù)資料
型號(hào)： TUA-6034
廠商： INFINEON TECHNOLOGIES AG
英文描述： 3-Band Digital TV / Set-Top-Box Tuner IC TAIFUN
中文描述： 3波段數(shù)字電視/設(shè)置機(jī)頂盒調(diào)諧器IC近日推出
文件頁(yè)數(shù)： 26/61頁(yè)
文件大?。?/td> 881K
代理商： TUA-6034
TUA6034, TUA6036
Functional Description
Specification
26
V 2.5, 2004-04-28
and ends with the stop condition. Start condition: SDA goes low, while SCL remains high.
Stop condition: SDA goes high while SCL remains high. All further information transfer
takes place during SCL = low, and the data is forwarded to the control logic on the
positive clock edge.
The table ’Bit Allocation’ (
see Table 8 on page 46
) should be referred to for the following
description. All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse,
during which the control logic returns the SDA line to low (acknowledge condition). The
first byte is comprised of seven address bits. These are used by the processor to select
the PLL from several peripheral components (address select). The LSB bit (R/W)
determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the first or
third data byte determines whether a divider ratio or control information is to follow. In
each case the second byte of the same data type has to follow the first byte. Appropriate
setting of the test bits will decide whether the band-switch byte or the auxiliary byte will
be transmitted (
see Table 11 on page 47
).
If the address byte indicates a READ operation, the PLL generates an acknowledge and
then shifts out the status byte onto the SDA line. If the processor generates an
acknowledge, a further status byte is output; otherwise the data line is released to allow
the processor to generate a stop condition. The status word consists of three bits from
the A/D converter, the lock flag and the power-on flag.
Four different chip addresses can be set by an appropriate DC level at pin AS (
see
Table 10 on page 47
).
While the supply voltage is applied, a power-on reset circuit prevents the PLL from
setting the SDA line to low, which would block the bus. The power-on reset flag POR is
set at power-on and if V
CC
falls below 3.2 V. It will be reset at the end of a READ
operation.
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