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Specification
25
V 2.5, 2004-04-28
TUA6034, TUA6036
Functional Description
If the VCO is not oscillating the PLL locks to a tuning voltage of 33V (V
TH
).
By means of control bits CP, T0, T1 and T2 the pump current can be switched between
four values by software. This programmability permits alteration of the control response
of the PLL in the locked-in state. In this way different VCO gains can be compensated,
for example.
The software controlled ports P0 to P4 are general purpose open-collector outputs. The
test bits T2, T1, T0 =1, 0, 0 switch the test signals f
div
(divided input signal) and f
ref
(i.e
.4 MHz / 64) to P0 and P1 respectively.
The lock detector resets the lock flag FL if the width of the charge pump current pulses
is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL = 1, the
maximum deviation of the input frequency from the programmed frequency is given by
f =
±
I
P
(K
VCO
/ f
XTAL
)
(C1+C2) / (C1
C2)
where I
P
is the charge pump current, K
VCO
the VCO gain, f
Xtal
the crystal oscillator
frequency and C
1
, C
2
the capacitances in the loop filter (
see Chapter 3
). As the charge
pump pulses at i.e. 62.5 kHz (= f
ref
), it takes a maximum of 16
μ
s for FL to be reset after
the loop has lost lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns
for eight consecutive f
ref
periods. Therefore it takes between 128 and 144
μ
s for FL to be
set after the loop regains lock.
2.4.3
The wide band AGC stage detects the level of the IF output signal and generates an
AGC voltage for gain control of the tuners input transistors. The AGC take-over and the
time constant are selectable by the I
2
C bus.
AGC
2.4.4
Data is exchanged between the processor and the PLL via the I
2
C bus. The clock is
generated by the processor (input SCL). Pin SDA functions as an input or output
depending on the direction of the data (open collector, external pull-up resistor). Both
inputs have a hysteresis and a low-pass characteristic, which enhance the noise
immunity of the I
2
C bus.
I
2
C-Bus Interface
The data from the processor pass through an I
2
C bus controller. Depending on their
function the data are subsequently stored in registers. If the bus is free, both lines will be
in the marking state (SDA, SCL are high). Each telegram begins with the start condition