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參數(shù)資料
| 型號： | TSX68C000MCB/C12.5A |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 12.5 MHz, MICROPROCESSOR, CDIP64 |
| 封裝： | CERAMIC, SDIP-64 |
| 文件頁數(shù)： | 53/54頁 |
| 文件大?。?/td> | 901K |
| 代理商： | TSX68C000MCB/C12.5A |
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8
0853B–HIREL–09/07
TS68C000
e2v semiconductors SAS 2007
This signal should not be asserted until the following four conditions are met:
1.
a bus grant has been received,
2.
address strobe is inactive which indicates that the microprocessor is not using the bus,
3.
data transfer acknowledge is Inactive which indicates that neither memory nor peripherals are
using the bus, and
4.
bus grant acknowledge is inactive which indicates that no other device is still claiming bus
mastership.
1.5.5
Interrupt Control (IPL0, IPL1, IPL2)
These Input pins indicate the encoded priority level of the device requesting an interrupt. Level seven is
the highest priority white level zero indicates that no interrupts are requested. Level seven cannot be
masked. The least significant bit is given in IPLO and the most significant bit is contained in IPL2. These
lines must remain stable until the processor signals interrupt acknowledge (FC0-FC2 are all high) to
insure that the interrupt is recognized.
1.5.6
System Control
The system control inputs are used to either reset or halt the processor and to indicate to the processor
that bus errors have occurred. The three system control inputs are explained in the following
paragraphs.
BUS ERROR (BERR)
This input informs the processor that there is a problem with the cycle currently being executed. Prob-
lems may be a result of:
1.
nonresponding devices,
2.
interrupt vector number acquisition failure,
3.
illegal access request as determined by a memory management unit, or
4.
other application dependent errors.
The bus error signal interacts with the halt signal to determine if the current bus cycle should be re-exe-
cuted or if exception processing should be performed.
RESET (RESET)
This bidirectional signal line acts to reset (start a system initialization sequence) to processor in
response to an external reset signal. An internally generated reset (result of a RESET instruction)
causes all external devices to be reset and the internal of the processor is not affected. A total system
reset (processor and external devices) is the result of external HALT and RESET signals applied at the
same time.
HALT (HALT)
When this bldirectional line is driven by an external device, it will cause the processor to stop at the com-
pletion of the current bus cycle. When the processor has been halted using this input, all controI signals
are inactive and all three-state lines are put in their high-impedance state.
When the processor has stopped executing Instructions, such as in a double bus fault condition, the
HALT line is driven by the processor to indicate to external devices that the processor has stopped.
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