參數(shù)資料
型號: TSX68C000MCB/C12.5A
廠商: E2V TECHNOLOGIES PLC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 12.5 MHz, MICROPROCESSOR, CDIP64
封裝: CERAMIC, SDIP-64
文件頁數(shù): 35/54頁
文件大?。?/td> 901K
代理商: TSX68C000MCB/C12.5A
40
0853B–HIREL–09/07
TS68C000
e2v semiconductors SAS 2007
2.7.3.3
Read Modify Write Cycle
The read-modify-write cycle performs a read, modifies the data in the arithmetic-logic unit, and writes the
data back to the same address. In the TS68C000, this cycle is indivisible in that the address strobe is
asserted throughout the entire cycle. The test and set (TAS) instruction uses this cycle to provide mean-
ingful communication between processors in a multiple processor environment. This Instruction is the
only instruction that uses the read-modify-write cycles and since the test and set instruction only oper-
ates on bytes, all read-modify-write are byte operations.
2.7.4
Instruction Set Overview
The TS68C000 instruction set is shown in Table 2-11. Some additional instructions are variations, or
sub-sets, of these and they appear in Table 2-12. Special emphasis has been given to the instruction
set's support of structured high-level languages to facilitate ease of programming. Each instruction, with
few exceptions, operates on bytes, words, and long words and most instructions can use any of the 14
addressing modes. Combining instruction types, data types, and addressing modes, over 1000 useful
instructions are provided. These instructions include signed and unsigned, multiply and divide, "quick"
arithmetic operations, BCD arithmetic, and expanded operations (through traps).
RESET
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS
Rest External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left with Extend
Rotate Right with Extend
Return from Exception
Return and Restore
Return form Subroutine
SBCD
Scc
STOP
SUB
SWAP
Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves
TAS
TRAP
TRAPV
TST
Test and Set Operand
Trap
Trap on Overflow
Test
UNLK
Unlink
Table 2-11.
Instruction Set Summary (Continued)
Mnemonic
Description
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