參數(shù)資料
型號(hào)： TSPC860SRMZPU40D4
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 40 MHz, RISC PROCESSOR, PBGA357
封裝： PLASTIC, BGA-357
文件頁數(shù)： 4/90頁
文件大小： 2351K
代理商： TSPC860SRMZPU40D4
12
TSPC860
2129A–HIREL–08/02
BG
Hi-Z
E2
Bidirectional
Bus Grant — Asserted low when the arbiter of the external bus
grants the bus to a specific device. When the TSPC860 is configured
to work with the internal arbiter, BG is configured as an output and
asserted every time the external master asserts BR and its priority
request is higher than any internal sources requiring a bus transfer.
However, when the TSPC860 is configured to work with an external
arbiter, BG is an input.
BB
Hi-Z
E1
Bidirectional
Active Pull-up
Bus Busy — Asserted low by a master to show that it owns the bus.
The TSPC860 asserts BB after the arbiter grants it bus ownership
and BB is negated.
FRZ
IRQ6
See Section
G3
Bidirectional
Freeze — Output asserted to indicate that the core is in debug
mode.
Interrupt Request 6 — One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core. Note that the interrupt request signal sent to the interrupt
controller is the logical AND of FRZ/IRQ6 (if defined as IRQ6) and
DP3/IRQ6 (if defined as IRQ6).
IRQ0
Hi-Z
V14
Input
Interrupt Request 0 — One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core.
IRQ1
Hi-Z
U14
Input
Interrupt Request 1 — One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core.
IRQ7
Hi-Z
W15
Input
Interrupt Request 7 — One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core.
CS(0-5)
High
C3, A2,
D4, E4,
A4, B4
Output
Chip Select — These outputs enable peripheral or memory devices
at programmed addresses if they are appropriately defined. CS0 can
be configured to be the global chip-select for the boot device.
CS6
CE1_B
High
D5
Output
Chip Select 6 — This output enables a peripheral or memory device
at a programmed address if defined appropriately in the BR6 and
OR6 in the memory controller.
Card Enable 1 Slot B — This output enables even byte transfers
when accesses to the PCMCIA Slot B are handled under the control
of the PCMCIA interface.
CS7
CE2_B
High
C4
Output
Chip Select 7 — This output enables a peripheral or memory device
at a programmed address if defined appropriately in the BR7 and
OR7 in the memory controller.
Card Enable 2 Slot B — This output enables odd byte transfers
when accesses to the PCMCIA Slot B are handled under the control
of the PCMCIA interface.
Table 1. Signal Descriptions (Continued)
Name
Reset
Number
Type
Description
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