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參數(shù)資料
| 型號(hào)： | TSL1401CS-LF |
| 廠商： | AMS-TAOS USA Inc |
| 文件頁數(shù)： | 3/19頁 |
| 文件大小： | 680K |
| 描述： | IC OPTO SENSOR ARRAY CSP PCB MT |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
| 其它名稱： | TSL1401-CS-LFDKR |
TSL1401CSLF
128 ?1 LINEAR SENSOR ARRAY WITH HOLD
TAOS072E APRIL 2007
2
r
r
Copyright E 2007, TAOS Inc.
The LUMENOLOGY r Company
www.taosinc.com
Terminal Functions
TERMINAL
NAME
NO.
DESCRIPTION
AO
6
Analog output
CLK
3
Clock. The clock controls charge transfer, pixel output, and reset.
GND
4, 5
Ground (substrate). All voltages are referenced to the substrate.
HOLD
2
Hold signal. HOLD freezes the result of a 128 pixel scan.
SI
1
Serial input. SI defines the start of the data-out sequence.
SO
7
Serial output. SO provides a signal to drive the SI input of another device
for cascading or as an end-of-data indication.
V
DD
8
Supply voltage. Supply voltage for both analog and digital circuits.
Detailed Description
The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog
switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the
integration time.
The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI. For proper operation, after meeting the minimum hold time condition,
SI must go low before the next rising edge of the clock. The signal called Hold is normally connected to SI. Then,
the rising edge of SI causes a HOLD condition. This causes all 128 sampling capacitors to be disconnected from
their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift
register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output
amplifier that generates a voltage on analog output AO. Simultaneously, during the first 18 clock cycles, all pixel
integrators are reset, and the next integration cycle begins on the 19
th
clock. On the 129
th
clock rising edge,
the SI pulse is clocked out of the shift register and the analog output AO assumes a high impedance state. Note
that this 129
th
clock pulse is required to terminate the output of the 128
th
pixel, and return the internal logic to
a known state. If a minimum integration time is desired, the next SI pulse may be presented after a minimum
delay of t
qt
(pixel charge transfer time) after the 129
th
clock pulse.
AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail
output voltage swing. With V
DD
= 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V
for saturation light level. When the device is not in the output phase, AO is in a high-impedance state.
The voltage developed at analog output (AO) is given by:
V
out
= V
drk
+ (R
e
) (E
e
)(t
int
)
where:
V
out
is the analog output voltage for white condition
V
drk
is the analog output voltage for dark condition
R
e
is the device responsivity for a given wavelength of light given in V/(糐/cm
2
)
E
e
is the incident irradiance in 糤/cm
2
t
int
is integration time in seconds
A 0.1 糉 bypass capacitor should be connected between V
DD
and ground as close as possible to the device.
The TSL1401CSLF is intended for use in a wide variety of applications, including: image scanning, mark and
code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and
optical linear and rotary encoding.
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