參數(shù)資料
型號(hào)： TSC2301IPAGRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 74/95頁(yè)
文件大小： 1322K
代理商： TSC2301IPAGRG4
www.ti.com
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Bits [7:6] — MCLK1-MCLK0
Master Clock Ratio. These two bits select the ratio of the audio master clock frequency to the audio sampling
frequency. The ratio can be 256 Fs, 384 Fs, or 512 Fs. The default master clock frequency is 256 Fs.
Table 35. Master Clock Ratio Selection
MCLK[1:0]
MCLK1
MCLK0
Description
0
Master clock (MCLK) = 256 x Fs (default)
0
1
Master clock (MCLK) = 384 x Fs
1
0
Master clock (MCLK) = 512 x Fs
1
Master clock (MCLK) = 256 x Fs
Bits [5:2] — I2SFS3-I2SFS0
I2S Sample Rate. These bits tell the internal PLL what the audio sampling rate is so that it provides the proper
clock rate to the data converters and the digital filters. The default sample rate is 48 kHz. See Table 36 for a
complete listing of available sampling rates. All combinations of I2SFS[3:0] not in Table 36 are not valid.
Table 36. I2S Sample Rate Select
I2SFS3
I2SFS2
I2SFS1
I2SFS0
Function
0
Fs = 48 kHz (default)
0
1
Fs = 44.1 kHz
0
1
0
Fs = 32 kHz
0
1
Fs = 24 kHz
0
1
0
Fs = 22.05 kHz
0
1
0
1
Fs = 16 kHz
0
1
0
Fs = 12 kHz
0
1
Fs = 11.05 kHz
1
0
Fs = 8 kHz
Bits [1:0] — I2SFM1-I2SFM0
I2S Format. These two bits select the I2S interface format. Both 16-bit and 20-bit data formats are supported. The
default format is 20-bit I2S.
Table 37. I2S Format Selection
I2SFM [1:0]
I2SFM1
I2SFM0
Description
0
DAC: 16-bit, MSB-first, right justified ADC: 16-bit, MSB-first, left justified
0
1
DAC: 20-bit, MSB-first, right justified ADC: 20-bit, MSB-first, left justified
1
0
DAC: 20-bit, MSB-first, left justified ADC: 20-bit, MSB-first, left justified
1
DAC: 20-bit, MSB-first, I2S (default) ADC: 20-bit, MSB-first, I2S (default)
ADC VOLUME CONTROL REGISTER (Page 2, Address 01h)
The ADC volume control register controls the independent programmable gain amplifiers (PGA's) on the left and
right channel inputs to the audio ADCs of the TSC2301. The gain of these PGAs can be adjusted from
-40 dB to 20 dB in 0.5-dB steps. The ADC inputs can also be hard-muted, or internally shorted to VCM so that no
input signal is seen.
The ADC volume control register is formatted as follows:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MSB
LSB
ADMU
ADVL
ADVL5
ADVL4
ADVL3
ADVL
ADMU
ADVR6 ADVR5 ADVR4 ADVR3 ADVR2 ADVR ADVR
L
6
2
1
0
R
1
0
76
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