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參數(shù)資料
| 型號： | TSB41AB3MPFPEP |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 44/55頁 |
| 文件大小： | 0K |
| 描述： | IC CABLE TXRX/ARBITER 80-HTQFP |
| 標準包裝： | 96 |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數(shù)： | 6/6 |
| 規(guī)程： | IEEE 1394 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-TQFP 裸露焊盤 |
| 供應商設備封裝： | 80-HTQFP（12x12） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 882 (CN2011-ZH PDF) |
| 其它名稱： | 296-23555 |
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TSB41AB3EP
IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER
SGLS122C JULY 2002 REVISED JUNE 2008
49
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interface reset and disable (continued)
The sequence of events for initialization of the PHY-LLC interface when the interface is in the nondifferentiated
mode of operation (ISO terminal is high) is as follows:1
a.
LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum
TRESTORE time, the LLC causes the interface to be initialized and restored to normal operation by
reasserting the LPS signal. (In Figure 27, the interface is shown in the disabled state with SYSCLK low
inactive. However, the interface initialization sequence described here is also executed if the interface
is merely reset but not yet disabled.)
b.
SYSCLK activated. If the interface is disabled, the PHY reactivates its SYSCLK output when it detects
that LPS has been reasserted. If the PHY has entered a low-power state, it takes between 5.3 ms to
7.3 ms for SYSCLK to be restored; if the PHY is not in a low-power state, SYSCLK is restored within
60 ns. The SYSCLK output is a 50% duty cycle square wave with a frequency of 49.152 MHz
±100 ppm
(period of 20.345 ns). During the first seven cycles of SYSCLK, the PHY continues to drive the CTL and
D terminals low. The LLC is also required to drive its CTL and D outputs low for one of the first six cycles
of SYSCLK but to otherwise place its CTL and D outputs in a high-impedance state. The LLC continues
to drive its LREQ output low during this time.
c.
Receive indicated. Upon the eighth SYSCLK cycle following reassertion of LPS, the PHY asserts the
receive state on the CTL lines and the data-on indication (all ones) on the D lines for one or more cycles.
d.
Initialization complete. The PHY asserts the Idle state on the CTL lines and logic 0 on the D lines. This
indicates that the PHY-LLC interface initialization is complete and normal operation may commence.
The PHY accepts requests from the LLC via the LREQ line.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSB41AB3PFP | 功能描述:緩沖器和線路驅動器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| TSB41AB3PFPG4 | 功能描述:1394 接口集成電路 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41BA3 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE1394B THREE PORT CABLE TRANSCEIVER/ARBITER |
| TSB41BA3A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSB41BA3A-EP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
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