參數(shù)資料
型號: TSB41AB3MPFPEP
廠商: Texas Instruments
文件頁數(shù): 41/55頁
文件大小: 0K
描述: IC CABLE TXRX/ARBITER 80-HTQFP
標準包裝: 96
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 6/6
規(guī)程: IEEE 1394
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 80-TQFP 裸露焊盤
供應商設備封裝: 80-HTQFP(12x12)
包裝: 托盤
產(chǎn)品目錄頁面: 882 (CN2011-ZH PDF)
其它名稱: 296-23555
TSB41AB3EP
IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER
SGLS122C JULY 2002 REVISED JUNE 2008
46
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interface reset and disable (continued)
The sequence of events for disabling the PHY-LLC interface when it is in the differentiated mode of operation
(ISO terminal is low) is as follows:1
a.
Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet
data reception and transmission via the CTL and D lines, and request activity via the LREQ line.
b.
LPS deasserted. The LLC deasserts the LPS signal and, within 1
s, terminates any request or interface
bus activity, and places its LREQ, CTL, and D outputs into a high-impedance state (the LLC terminates
any output signal activity such that signals end in a logic 0 state).
c.
Interface reset. After TLPS_RESET time, the PHY determines that LPS is inactive, terminates any
interface bus activity, and places its CTL and D outputs into a high-impedance state (the PHY
terminates any output signal activity such that signals end in a logic 0 state). The PHY-LLC interface
is now in the reset state.
d.
Interface disabled. If the LPS signal remain inactive for TLPS_DISABLE time, the PHY terminates
SYSCLK activity by placing the SYSCLK output into a high-impedance state. The PHY-LLC interface
is now in the disabled state.
SYSCLK
ISO
(high)
(a)
(c)
(b)
CTL0, CTL1
D0 D7
LREQ
LPS
TLPS_RESET
(d)
TLPS_DISABLE
Figure 26. Interface Disable, ISO High
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