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參數(shù)資料
| 型號： | TSA1002IFT |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | 7 X 7 MM, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 236K |
| 代理商： | TSA1002IFT |
Obsolete
Product(s)
- Obsolete
Product(s)
TSA1002
17/20
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Clock input
The quality of your converter is very dependant on
your clock input accuracy, in terms of aperture
jitter; the use of low jitter crystal controlled
oscillator is recommended.
The clock power supplies must be separated from
the ADC output ones to avoid digital noise
modulation at the output.
It is recommended to keep the circuit clocked, to
avoid random states, before applying the supply
voltages.
Layout precautions
To use the ADC circuits in the best manner at high
frequencies, some precautions have to be taken
for power supplies:
- First of all, the implementation of 4 separate
proper supplies and ground planes (analog,
digital, internal and external buffer ones) on the
PCB is recommended for high speed circuit
applications to provide low inductance and low
resistance common return.
The separation of the analog signal from the
digital part is essential to prevent noise from
coupling onto the input signal.
- Power supply bypass capacitors must be placed
as close as possible to the IC pins in order to
improve high frequency bypassing and reduce
harmonic distortion.
- Proper termination of all inputs and outputs is
needed; with output termination resistors, the
amplifier load will be only resistive and the stability
of the amplifier will be improved. All leads must be
wide and as short as possible especially for the
analog input in order to decrease parasitic
capacitance and inductance.
- To keep the capacitive loading as low as
possible at digital outputs, short lead lengths of
routing are essential to minimize currents when
the output changes. To minimize this output
capacitance, buffers or latches close to the output
pins will relax this constraint.
- Choose component sizes as small as possible
(SMD).
EVAL1002 evaluation board
The characterization of the board has been made
with a fully ADC devoted test bench as shown on
Figure 11. The analog signal must be filtered to be
very pure.
The dataready signal is the acquisition clock of the
logic analyzer.
The ADC digital outputs are latched by the
74LCX573 octal buffers.
All characterization measurement has been made
with an input amplitude of +0.2dB for static
parameters and -0.5dB for dynamic parameters.
Figure 11 : Analog to Digital Converter characterization bench
Sine Wave
Generator
HP8644
ADC
evaluation
board
Pulse
Generator
Logic
Analyzer
Sine Wave
Generator
HP8644
HP8133
Vin
Clk
Data
Clk
PC
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| TSA1005-20IFT | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| TSA1005-40IFT | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| TSA1005I-40IF | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| TSA1005-20IF | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| TSA1005-40IF | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSA1005 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DUAL-CHANNEL, 10-BIT, 20/40MSPS A/D CONVERTER |
| TSA1005-20IF | 制造商:STMicroelectronics 功能描述:ADC DUAL PIPELINED 20MSPS 10-BIT PARALLEL 48TQFP - Trays |
| TSA1005-20IFT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DUAL-CHANNEL, 10-BIT, 20/40MSPS A/D CONVERTER |
| TSA1005-40IF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog to Digital Converter |
| TSA1005-40IFT | 功能描述:模數(shù)轉換器 - ADC DUAL CHANNEL 10 BIT 20/40MSPS A/D CONVTR RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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