參數(shù)資料
型號： TS87C51RC2-MCE
廠商： International Rectifier
英文描述： High Performance 8-bit Microcontroller
中文描述： 高性能8位微控制器
文件頁數(shù)： 26/85頁
文件大?。?/td> 762K
代理商： TS87C51RC2-MCE
26
4188E–8051–08/06
AT/TS8xC51Rx2
The CIDL bit which allows the PCA to stop during idle mode.
The WDTE bit which enables or disables the watchdog function on module 4.
The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON
SFR) to be set when the PCA timer overflows.
The CCON SFR
contains the run control bit for the PCA and the flags for the PCA timer (CF)
and each module (Refer to Table 6-5).
Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this
bit.
Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be
generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by
software.
Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and
are set by hardware when either a match or a capture occurs. These flags also can only be
cleared by software.
Table 6-5.
CCON: PCA Counter Control Register
The watchdog timer
function is implemented in module 4 (See Figure 6-7).
The PCA interrupt
system is shown in Figure 6-5.
CCON
Address 0D8H
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0
Reset value
0
0
X
0
0
0
0
0
Symbol
Function
CF
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags
an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be
cleared by software.
CR
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by
software to turn the PCA counter off.
-
Not implemented, reserved for future use.
(1)
1.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0,
and its active value will be 1. The value read from a reserved bit is indeterminate.
CCF4
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by
software.
CCF3
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by
software.
CCF2
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by
software.
CCF1
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by
software.
CCF0
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by
software.
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