參數(shù)資料
型號(hào)： TS86101G2BVGL
廠商： ATMEL CORP
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 10-BIT DAC, PBGA255
封裝： CBGA-255
文件頁(yè)數(shù)： 16/57頁(yè)
文件大?。?/td> 1119K
代理商： TS86101G2BVGL
23
5343C–BDC–03/06
TS86101G2B
Case 1:
If the D_CK clock edge occurs before the forbidden zone, data N will be transferred internally
from the first to the second bank of latch (see Figure 8-2 on page 30).
Case 2:
If the D_CK clock edge occurs after the forbidden zone, data N +1 will be transferred internally
from the first to the second bank of latch (see Figure 8-2 on page 30).
5.3.1
Tuning the DSP Clock Output Phase
The DSP clock output phase may be tuned over a range of 3.1 ns in 15 discrete steps of 200 ps
each, plus a propagation delay of 2.1 ns (the 2.10 ns value is an absolute timing value measured
from CW_IN input ball to DSP Clock output ball), by correctly setting the 4-bit address input
CS_0, CS_1, CS_2 and CS_3 from 0000 to 1111:
– 0000: 2.1 ns + 0
– 0001: 2.1 ns + 200 ps
–…
– 1111: 2.1 ns + 3.1 ns
5.3.2
Analog Output Data Switching Information
The analog output data changes on the CW_IN master clock’s rising edge, after one clock cycle
pipeline delay, plus TOD (output propagation delay). TOD includes the following:
Propagation time delays of the packaging accesses
The DAC’s core internal conversion time and other internal propagation delays
The typical value of TOD is 3.7 ns, assuming a 50
// 2 pF load.
6.
Main Features of the TS86101G2B
6.1
Input MUX
The 4:1 integrated input MUX of the TS86101G2B provides the user with the capacity to apply
an input data rate four times lower than the effective sampling frequency used:
Data rate = Fs/4 = F(DSP_CK) = F(D_CK)
Where:
– F(DSP_CK) is the frequency of the DSP output clock
– F(D_CK) is the frequency of the Data Ready input clock
Since this input MUX is not programmable, all four ports must be used for proper operation of
the DAC.
相關(guān)PDF資料
PDF描述
TS86101G2BMGS SERIAL INPUT LOADING, 10-BIT DAC, PBGA255
TS86101G2BMGS PARALLEL, WORD INPUT LOADING, 10-BIT DAC, CBGA255
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