參數(shù)資料
型號(hào): TS86101G2BMGS
廠商: E2V TECHNOLOGIES PLC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 10-BIT DAC, CBGA255
封裝: CI-CGA, 255 PIN
文件頁(yè)數(shù): 11/57頁(yè)
文件大?。?/td> 1030K
代理商: TS86101G2BMGS
19
0992D–BDC–04/09
e2v semiconductors SAS 2009
TS86101G2B
Analog Outputs
OUT_T
T10
In-phase (+) analog output signal
OUT_F
T9
Inverted phase (-) of analog output signal (Vout)
Clock Inputs
D_CK_T
A8
In phase (+) PECL/LVDS Data Ready clock
input signal. The digital data is loaded on the
rising edge of the Data Ready clock signal
D_CK_F
A9
Inverted phase (-) of PECL/LVDS Data Ready
clock input signal
CW_IN_T
T6
In-phase (+) of ECL/PECL/LVDS master clock
input signal. The analog output is sampled and
held on the rising edge of the CW_IN_T signal
CW_IN_F
T7
Inverted phase (-) of ECL/PECL/LVDS master
clock input signal
DSP Clock Outputs
DSP_CK_T
R1
In-phase (+) PECL/LVDS DSP clock output
signal. The digital DSP clock
DSP_CK_F
P1
Inverted phase (-) of PECL/LVDS DSP clock
output signal
Additional Functions
CS_0, CS_1, CS_2, CS_3
R12, T12, R13, T13
Selectable shift for DSP output clock (adjust
TDSP)
0 = TTL low or GND
1 = TTL high or left open
DIODE
T15
Die junction temperature monitoring
GA
P16
Gain adjust (to be connected to the REF pin)
Ref
R16
Reference for gain
TP
A16
Non-connected pin
Table 4-1.
TS86101G2B Pin Description (Continued)
Symbol
Pin number
Function
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