參數(shù)資料
型號: TS83148MZ
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDSO28
封裝: CERAMIC, DFP-28
文件頁數(shù): 11/16頁
文件大?。?/td> 551K
代理商: TS83148MZ
TS83148
4/16
Min.
Unit
Max.
Typ.
Test level
Tamb
Symbol
Parameter
DYNAMIC CHARACTERISTICS
Transient response
Vin = 1.9 Vpp
TR
15
ns
Overvoltage recovery time
ORT
25
ns
Maximum clock frequency
FS
60
MSPS
Minimum clock frequency
FS
0.5
1
MSPS
Spurious Free Dynamic Range
SFDR
FS = 50 MSPS ; FIN = 10 MHz
60
dB
FS = 40 MSPS ; FIN = 20 MHz
58
dB
Power Supply Rejection Ratio
PSRR
TBD
mV/V
Signal to noise ratio
FS = 50 MSPS, FIN = 10 MHz
FS = 40 MSPS, FIN = 20 MHz
SNR
48
45
dB
Total harmonic distorsion
FS = 50 MSPS, FIN = 10 MHz
FS = 40 MSPS, FIN = 20 MHz
THD
51
43
dBc
Signal to noise and distorsion ratio
FS = 50 MSPS, FIN = 10 MHz
FS = 40 MSPS, FIN = 20 MHz
SINAD
47
41
dB
Effective number of bits
FS = 50 MSPS, FIN = 10 MHz
FS = 40 MSPS, FIN = 20 MHz
ENOB
7.5
7
bits
Dual tone intermodulation
(Fin1 = 9.9 MHz@1/2 FS
(Fin2 = 10.1 MHz@1/2 FS)
IMD
54
dB
Bit Error Rate
FS = 40 MSPS, FIN = 10 MHz
Output error >
±16 LSB
BER
10–10
error/
sample
POWER REQUIREMENTS
Power supply
AVcc
DVcc
full
4.75
5
5.25
V
Power dissipation Normal mode
Nap mode
190
40
TBD
mW
THERMAL RESISTANCES
SOIC 28 (plastic) Junction to ambient
Junction to case
qJA
qJC
57
10
°C/W
CDFP 28 (ceramic)Junction to ambient
Junction to case
qJA
qJC
56
13
°C/W
Note :
Analog input range (offset only) can be adjusted using VREF input : VREF – 0.5 V < VIN < VREF + 0.5 V ; 2.3 V <VREF< 3.3 V
相關PDF資料
PDF描述
TS83148VS 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TS83148VZT 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDFP28
TS83148MZB/T 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDSO28
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