參數(shù)資料
型號(hào)： TS8308500VGL
廠商： E2V TECHNOLOGIES PLC
元件分類(lèi)： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, CBGA68
封裝： 11 X 11 MM, 1.27MM PITCH, CERAMIC, BGA-68
文件頁(yè)數(shù)： 17/50頁(yè)
文件大?。?/td> 491K
代理商： TS8308500VGL
24
TS8308500
2193A–BDC–04/03
Data Ready Output
Signal Restart
The Data Ready output signal restarts on the DRRB command’s rising edge, ECL logical high
levels (-0.8V). DRRB may also be grounded, or is allowed to float, for a normal free running
Data Ready output signal.
The Data Ready signal restart sequence depends on the logical level of the external encoding
clock, at DRRB rising edge instant:
The DRRB rising edge occurs when the external encoding clock input (CLK,CLKB) is
LOW: The Data Ready output’s first rising edge occurs after half a clock period on the
clock falling edge, after a delay time TDR = 1320 ps already defined hereabove.
The DRRB rising edge occurs when external encoding clock input (CLK,CLKB) is HIGH:
The Data Ready output’s first rising edge occurs after one clock period on the clock falling
edge, and a delay TDR = 1320 ps.
Consequently, as the analog input is sampled on the clock’s rising edge, the first digitized data
corresponding to the first acquisition (N) after a Data Ready signal restart (rising edge) is
always strobed by the third rising edge of the Data Ready signal.
The time delay (TD1) is specified between the last point of a change in the differential output
data (zero crossing point) to the rising or falling edge of the differential Data Ready signal
(DR,DRB) (zero crossing point).
Note:
1. For normal initialization of the Data Ready output signal, the external encoding clock signal
frequency and level must be controlled. The minimum encoding clock sampling rate for the
ADC is 10 Msps and consequently the clock cannot be stopped.
2. One single pin is used for both the DRRB input command and die junction temperature
monitoring. Pin denomination will be DRRB/DIOD. (On former versions the denomination
was DIOD.). Temperature monitoring and Data Ready control by DRRB is not possible
simultaneously.
Analog Inputs (V
IN,
V
INB)
The analog input Full Scale range is 0.5V, or -2 dBm into the 50
termination resistor.
In differential mode input configuration, that means 0.25V on each input, or ±125 mV around
0V. The input common mode is ground.
The typical input capacitance is 3 pF for TS8308500 in a CBGA package.
Differential Input
Voltage Span
Figure 28. Differential Input Voltage Span
-125
125
[mV]
-250 mV
VIN
(VIN, VINB) =
±250 mV = 500 mV diff
500 mV
Full Scale
analog input
t
VINB
0V
250 mV
相關(guān)PDF資料
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