參數(shù)資料
型號(hào)： TS8308500VGL
廠商： E2V TECHNOLOGIES PLC
元件分類： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, CBGA68
封裝： 11 X 11 MM, 1.27MM PITCH, CERAMIC, BGA-68
文件頁(yè)數(shù)： 16/50頁(yè)
文件大?。?/td> 491K
代理商： TS8308500VGL
23
TS8308500
2193A–BDC–04/03
Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The
same is true for the TOD and TDR maximum values.
In other words:
–
If TOD is at 1150 ps, TDR will not be at 1620 ps (maximum time delay for TDR).
–
If TOD is at 1660 ps, TDR will not be at 1110 ps (minimum time delay for TDR).
However, external TOD-TDR values may be dictated by total digital data skews
between every TODs (each digital data) and TDR: MCM board , bonding wires and
output lines lengths differences, and output termination impedance mismatches.
The external (on board) skew effect has NOT been taken into account for the specification of
the minimum and maximum values for TOD-TDR.
Principle of Operation
The Analog input is sampled on the rising edge of the external clock input (CLK, CLKB) after
TA (aperture delay) of typically 250 ps .
The digitized data is available after 4 clock periods latency (pipeline delay (TPD), on clock ris-
ing edge, after 1360 ps typical propagation delay TOD.)
The Data Ready differential output signal frequency (DR, DRB) is half the external clock fre-
quency, that is it switches at the same rate as the digital outputs.
The Data Ready output signal (DR, DRB) switches on the external clock falling edge after a
propagation delay TDR of typically 1320 ps.
A Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) is
available for initializing the differential Data Ready output signal (DR, DRB).
This feature is mandatory in certain applications using interleaved ADCs or using a single
ADC with demultiplexed outputs. Actually, without Data Ready signal initialization, it is impos-
sible to store the output digital data in a defined order.
Principle of Data
Ready Signal
Control by DRRB
Input Command
Data Ready Output
Signal Reset
The Data Ready signal is reset on the falling edge of the DRRB input command, on the ECL
logical low level (-1.8V). DRRB may also be tied to V
EE = -5V for Data Ready output signal
Master Reset. So long as DRRB remains at a logical low level, (or tied to V
EE = -5V), the Data
Ready output remains at logical zero and is independent of the external free running encoding
clock.
The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 720 ps typical.
TRDR is measured between the -1.3V point of the falling edge of the DRRB input command
and the zero crossing point of the differential Data Ready output signal (DR, DRB).
The Data Ready Reset command may be a pulse of 1 ns minimum time width.
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