參數(shù)資料
型號: TS8308500CGL
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, CBGA68
封裝: 11 X 11 MM, 1.27MM PITCH, CERAMIC, BGA-68
文件頁數(shù): 12/50頁
文件大?。?/td> 491K
代理商: TS8308500CGL
2
TS8308500
2193A–BDC–04/03
Functional
Description
Block Diagram
Figure 1. Simplified Block Diagram
Functional
Description
The TS8308500 is an 8-bit 500 Msps ADC based on an advanced high-speed bipolar technol-
ogy featuring a cutoff frequency of 25 GHz.
The TS8308500 includes a front-end master/slave Track and Hold stage (S/H), followed by an
analog encoding stage and interpolation circuitry.
Successive banks of latches are regenerating the analog residues into logical data before
entering an error correction circuitry and a resynchronization stage followed by 75
differential
output buffers.
The TS8308500 works in fully differential mode from analog inputs up to digital outputs.
The TS8308500 features a full-power input bandwidth of 1.3 GHz.
Control pin GORB is provided to select either the Gray or Binary data output format.
The gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8308500.
The TS8308500 uses only vertical isolated NPN transistors together with oxide isolated poly-
silicon resistors, which allow enhanced radiation tolerance (no performance drift measured at
150 kRad total dose).
Master/Slave Track & Hold Amplifier
VIN, VINB
Clock
Buffer
GAIN
GORB
DATA, DATAB OR, ORB
DRRB DR, DRB
CLK, CLKB
4
5
4
5
8
Resistor
Chain
Analog
Encoding
Block
Interpolation
Stages
Regeneration
Latches
Error Correction &
Decode Logic
Output Latches &
Buffers
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