參數(shù)資料
型號： TS80L186EB16
廠商： Intel Corp.
英文描述： 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
中文描述： 16位高集成嵌入式處理器
文件頁數(shù)： 11/59頁
文件大?。?/td> 779K
代理商： TS80L186EB16
80C186EB/80C188EB, 80L186EB/80L188EB
Table 3. Pin Descriptions
(Continued)
Pin
Name
Pin
Type
Input
Type
Output
States
Description
A18:16
A19/ONCE
(A15:A8)
(A18:16)
(A19/ONCE)
I/O
A(L)
H(Z)
R(WH)
P(X)
These pins provide multiplexed
Address
during the address
phase of the bus cycle. Address bits 16 through 19 are presented
on these pins and can be latched using ALE. These pins are
driven to a logic 0 during the data phase of the bus cycle. On the
80C188EB, A15–A8 provide valid address information for the
entire bus cycle. During a processor reset (RESIN active), A19/
ONCE is used to enable ONCE mode. A18:16 must not be driven
low during reset or improper operation may result.
S2:0
O
D
H(Z)
R(Z)
P(1)
Bus cycle
Status
are encoded on these pins to provide bus
transaction information. S2:0 are encoded as follows:
S2
S1
S0
Bus Cycle Initiated
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O
Write I/O
Processor HALT
Queue Instruction Fetch
Read Memory
Write Memory
Passive (no bus activity)
ALE
O
D
H(0)
R(0)
P(0)
Address Latch Enable
output is used to strobe address
information into a transparent type latch during the address phase
of the bus cycle.
BHE
(RFSH)
O
D
H(Z)
R(Z)
P(X)
Byte High Enable
output to indicate that the bus cycle in progress
is transferring data over the upper half of the data bus. BHE and
A0 have the following logical encoding
A0
BHE
Encoding
(for the 80C186EB/80L186EB only)
0
0
1
1
0
1
0
1
Word Transfer
Even Byte Transfer
Odd Byte Transfer
Refresh Operation
On the 80C188EB/80L188EB, RFSH is asserted low to indicate a
refresh bus cycle.
RD
O
D
H(Z)
R(Z)
P(1)
ReaD
output signals that the accessed memory or I/O device
must drive data information onto the data bus.
WR
O
D
H(Z)
R(Z)
P(1)
WRite
output signals that data available on the data bus are to be
written into the accessed memory or I/O device.
READY
I
A(L)
S(L)
D
READY
input to signal the completion of a bus cycle. READY
must be active to terminate any bus cycle, unless it is ignored by
correctly programming the Chip-Select Unit.
DEN
O
D
H(Z)
R(Z)
P(1)
Data ENable
output to control the enable of bi-directional
transceivers in a buffered system. DEN is active only when data is
to be transferred on the bus.
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.
11
11
相關(guān)PDF資料
PDF描述
TS80L186EB8 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
TS80L188EB13 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
TS80L188EB8 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
TS80C186EB20 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
TS80C186EB25 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TS80L188EB13 功能描述:IC MPU 16-BIT 3V 13MHZ 80-MQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤
TS80L188EC13 功能描述:IC MPU 16-BIT 3V 13MHZ 100-MQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤
TS-80S 制造商:Ultimate Support Systems 功能描述:Silver Original Speaker Stand 制造商:ULTIMATE SUPPORT 功能描述:ORIGINAL SPEAKER STAND SILVER
TS81 功能描述:T-STRUT 1" X 8.12" ALUMINUM RoHS:是 類別:盒，外殼，支架 >> 卡架 - 配件 系列:VectorPak™ 標準包裝:1 系列:VectorPak™ 附件類型:EFP 模塊 適用于相關(guān)產(chǎn)品:PCB
TS810 制造商:TSC 制造商全稱:Taiwan Semiconductor Company, Ltd 功能描述:Microprocessor Reset Circuit
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*