參數(shù)資料
型號(hào)： TS80C51RD2-VIE
廠商： International Rectifier
英文描述： High Performance 8-bit Microcontroller
中文描述： 高性能8位微控制器
文件頁數(shù)： 44/85頁
文件大?。?/td> 762K
代理商： TS80C51RD2-VIE
44
4188E–8051–08/06
AT/TS8xC51Rx2
6.6
Idle Mode
An instruction that sets PCON.0 causes that to be the last instruction executed before going into
the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the
interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack
Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain
their data during Idle. The port pins hold the logical states they had at the time Idle was acti-
vated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0
to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and follow-
ing RETI the next instruction to be executed will be the one following the instruction that put the
device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during nor-
mal operation or during an Idle. For example, an instruction that activates Idle can also set one
or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can exam-
ine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is
still running, the hardware reset needs to be held active for only two machine cycles (24 oscilla-
tor periods) to complete the reset.
6.7
Power-down Mode
To save maximum power, a power-down mode can be invoked by software (Refer to
Table 6-15
,
PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-down
mode is the last instruction executed. The internal RAM and SFRs retain their value until the
power-down mode is terminated. V
CC
can be lowered to save further power. Either a hardware
reset or an external interrupt can cause an exit from power-down. To properly terminate power-
down, the reset or external interrupt should not be executed before V
CC
is restored to its normal
operating level and must be held active long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt
must be enabled and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed
in Figure 6-14. When both interrupts are enabled, the oscillator restarts as soon as one of the
two inputs is held low and power down exit will be completed when the first input will be
released. In this case the higher priority interrupt service routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the one fol-
lowing the instruction that put TS80C51Rx2 into power-down mode.
相關(guān)PDF資料
PDF描述
TS83C51RB2-LCB High Performance 8-bit Microcontroller
TS83C51RB2-LCE High Performance 8-bit Microcontroller
TS83C51RB2-LIB High Performance 8-bit Microcontroller
TS83C51RB2-LIE High Performance 8-bit Microcontroller
TS83C51RB2-MCB High Performance 8-bit Microcontroller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TS80C51RD2-VIEB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
TS80C51RD2-VIED 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
TS80C51RD2-VIER 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
TS80C51RD2-VIL 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance 8-bit Microcontroller
TS80C51RD2-VILB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
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