![](http://datasheet.mmic.net.cn/370000/TS83C51RC2-LCE_datasheet_16739858/TS83C51RC2-LCE_61.png)
61
4188E–8051–08/06
AT/TS8xC51Rx2
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V
OL
s of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed
0.45V with maxi V
OL
peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
6. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin: 10 mA
Maximum I
OL
per 8-bit port:
Port 0: 26 mA
Ports 1, 2, 3 and 4 and 5 when available: 15 mA
Maximum total I
OL
for all output pins: 71 mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7. For other values, please contact your sales office.
8. Operating I
CC
is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
= 5 ns (see Figure 11-5.), V
IL
=
V
SS
+ 0.5 V,
V
IH
= V
CC
- 0.5V; XTAL2 N.C.; EA = Port 0 = V
CC
; RST = V
SS
. The internal ROM runs the code 80 FE (label: SJMP label). I
CC
would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is
the worst case.
Figure 11-1.
I
CC
Test Condition, under reset
Figure 11-2.
Operating I
CC
Test Condition
EA
V
CC
V
CC
I
CC
(NC)
CLOCK
SIGNAL
V
CC
All other pins are disconnected.
RST
XTAL2
XTAL1
V
SS
V
CC
P0
EA
V
CC
V
CC
I
CC
(NC)
CLOCK
SIGNAL
All other pins are disconnected.
RST
XTAL2
XTAL1
V
SS
V
CC
P0
Reset = Vss after a high pulse
during at least 24 clock cycles