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參數(shù)資料
| 型號： | TS68C000DESC02ZCA |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 10 MHz, MICROPROCESSOR, CQFP68 |
| 封裝： | GOLD PLATED, CERAMIC, QFP-68 |
| 文件頁數(shù)： | 52/52頁 |
| 文件大?。?/td> | 667K |
| 代理商： | TS68C000DESC02ZCA |
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9
2170A–HIREL–09/05
TS68C000
1.5.0.7
EF 6800 Peripheral Control
These control signals are used to allow the interfacing of synchronous EF 6800 peripheral
devices with the asynchronous TS68C000. These signals are explained in the following
paragraphs.
ENABLE (E)
This signal is the standard enable signal common to all EF 6800 type peripheral devices. The
period for this output is ten TS68C000 clock periods (six clocks low, four clocks high). Enable is
generated by an internal ring counter which may come up in any state (i.e., at power on, it Is
impossible to guarantee phase relationship of E to CLK). E is a free-running crack and runs
regardless of the state of the bus on the MPU.
VALID PERIPHERAL ADDRESS (VPA)
This input indicates that the device or region addressed is an TS68000 Family device and that
data transfer should be synchronized with the enable (E) signal. This Input also indicates that
the processor should use automatic vectoring for an interrupt during an IACK cycle.
VALID MEMORY ADDRESS (VMA)
This output is used to indicate to TS68000 peripheral devices that there is a valid address on the
address bus and the processor is synchronized to enable. This signal only responds to a valid
peripheral address (VPA) input which indicates that the peripheral is an TS68000 Family device.
1.5.0.8
Processor Status (FC0, FC1, FC2)
These function code outputs indicate the state (user or supervisor) and the cycle type currently
being executed, as shown in Table 1-3. The information indicated by the function code outputs is
valid whenever address strobe (AS) is active.
1.5.0.9
Clock (CLK)
The clock input is a TTL-compatible signal that is internally buffered for development of the inter-
nal clocks needed by the processor. The clock input should not be gated off at any time and the
clock signal must conform to minimum and maximum pulse width times. The clock is a constant
frequency square wave with no stretching or shaping techniques required.
Table 1-3.
Processor Status Table
Function Code Output
Cycle Time
FC2
FC1
FC0
Low
(Undefined, reserved)
Low
High
User data
Low
High
Low
User program
Low
High
(Undefined, reserved)
High
Low
(Undefined, reserved)
High
Low
High
Supervisor data
High
Low
Supervisor program
High
Interrupt acknowledge
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TS68C000DESC03UAA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER HCMOS 16/32 BIT MICROPROCESSOR |
| TS68C000DESC03UCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER HCMOS 16/32 BIT MICROPROCESSOR |
| TS68C000DESC03XAA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER HCMOS 16/32 BIT MICROPROCESSOR |
| TS68C000DESC03XCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER HCMOS 16/32 BIT MICROPROCESSOR |
| TS68C000DESC03YAA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER HCMOS 16/32 BIT MICROPROCESSOR |
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