參數(shù)資料
型號： TPS65950ZXNT
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA209
封裝： 7 X 7 MM, 0.40 MM PITCH, PLASTIC, BGA-209
文件頁數(shù)： 10/167頁
文件大?。?/td> 2566K
代理商： TPS65950ZXNT
7.2.4.2 LS/FS Single-Ended Receivers
7.2.4.3 LS/FS Differential Receiver
TPS65950
Integrated Power Management/Audio Codec
www.ti.com
SWCS032 – OCTOBER 2008
Table 7-6. 5V-Tolerant Electrical Summary
Parameter
Comments
Min(1)
Typ(2)
Max(3)
Unit
Continuous short-circuit
50% TX/50% RX/50% LS/50% FS/VBUS = 5.25
DCSTRESS
24
h
stress
V
tHI = 60 ns/tLO = 100 ns/tR = tF = 4 ns/
Worst case overshoot and
ACSTRESS
VHI = 4.6 V/VLO = –1.0 V/RSRC = 39/
24
h
undershoot stress
50% TX/50% RX/VBUS = 5.25 V
Internal DP/DM stress
VDX_STRESS
Force 5.25 V VBUS/DP/DM
4.3
V
voltage
V3P1_STRES
V3P1 stress voltage
Force 5.25 V VBUS/DP/DM/ID
3.6
V
S
DP/DM input stress current
IDX_STRESS
Force 5.25 V VBUS/DP/DM
30
mA
ID input stress current
IID_STRESS
Force 5.25 V VBUS/DP/DM/ID
25
A
(1)
Min = Minimum value
(2)
Typ = Typical value
(3)
Max = Maximum value
In addition to the differential receiver, there is a single-ended receiver (SE–, SE+) for each of the two data
lines D+/–. The main purpose of the single-ended receivers is to qualify the D+ and D– signals in the
FS/LS modes of operation. Table 7-7 lists the parameters of the LS/FS single-ended receivers.
Table 7-7. LS/FS Single-Ended Receivers
Parameter
Comments
Min(1)
Typ(2) Max(3)
Unit
USB Single-Ended Receivers
Skew between VP and VM
SKWVP_VM
Driver outputs unloaded
–2
0
2
ns
Single-ended hysteresis
VSE_HYS
0
mV
High (driven)
VIH
2
V
Low
VIL
0.8
V
Switching threshold
VTH
0.8
2
V
UART Receiver CEA
VIH_SER
DP_PULLDOWN asserted
2
V
Serial interface input low
VIL_SER
DP_PULLDOWN asserted
0.8
V
Switching threshold
VTH
0.8
2
V
UART Receiver MCPC From DP.RXD
MCPC DP pullup
RMCPCDP
Internal pullup
4.7k
10k
Open-drain input high level
ZIH
Internal MCPC DP pullup asserted
Open
External open-drain NMOS impedance to ground.
Open-drain input low level
ZIL
100
With internal MCPC DP pullup asserted.
Output high level
VOH (*)
At DATA1 pin
VIO – 0.45
V
Output low level
VOL
At DATA1 pin
0.45
V
(1)
Min = Minimum value
(2)
Typ = Typical value
(3)
Max = Maximum value
A differential input receiver (RX) retrieves the LS/FS differential data signaling. The differential voltage on
the line is converted to digital data by a differential comparator on DP/DM. This data is then sent to a
clock and data recovery circuit that recovers the clock from the data. In an additional serial mode, the
differential data is directly output on the RXRCV pin. Table 7-8 lists the parameters of the LS/FS
differential receiver.
USB HS 2.0 OTG Transceiver
107
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