參數(shù)資料
型號： TPS65950ZXNR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA209
封裝： 7 X 7 MM, 0.40 MM PITCH, PLASTIC, BGA-209
文件頁數(shù)： 9/167頁
文件大?。?/td> 2566K
代理商： TPS65950ZXNR
7.2.4
PHY Electrical Characteristics
7.2.4.1 5-V Tolerance
TPS65950
Integrated Power Management/Audio Codec
SWCS032 – OCTOBER 2008
www.ti.com
Table 7-4. HS USB Interface Timing Requirement Parameters
Notation
Parameter
Min(1)
Max(2)
Unit
HSU4
ts(STPV-CLKH)
Setup time, STP valid before UCLK rising edge
6
ns
HSU5
th(CLKH-STPIV)
Hold time, STP valid after UCLK rising edge
0
ns
HSU6
ts(DATAV-CLKH)
Setup time, DATA[0:7] valid before UCLK rising edge
6
ns
HSU7
th(CLKH-DATIV)
Hold time, DATA[0:7] valid after UCLK rising edge
0
ns
(1)
Min = Minimum value
(2)
Max = Maximum value
Table 7-5. HS USB Interface Switching Requirement Parameters(1)
Notation
Parameter
Min(2)
Typ(3)
Max(4)
Unit
HSU0
fp(CLK)
UCLK clock frequency
Steady state
58.42
60
61.67
MHz
HSU1
tW(CLK)
UCLK duty cycle
Steady state
48.3%
50%
51.7%
Delay time, UCLK rising edge to DIR
Steady state
0
9
td(CLKH-DIR)
ns
transition
HSU2
Delay time, UCLK rising edge to NXT
Steady state
0
9
td(CLKH-NXTV)
ns
transition
Delay time, UCLK rising edge to DATA[0:7] Steady state
0
9
HSU3
td(CLKH-DATV)
ns
transition
(1)
The capacitive load for output data and control load is 10 pF (rising and falling time is 2 ns).
The capacitive load for the CLK port is 6 pF (rising and falling time is 1 ns).
The HS USB interface has only one state: steady state.
(2)
Min = Minimum value
(3)
Typ = Typical value
(4)
Max = Maximum value
The PHY is the physical signaling layer of the USB 2.0. It contains the drivers and receivers required for
physical data and protocol signaling on the DP and DM lines.
The PHY interfaces to the USB controller through UTMI.
There are two main classes of transmitters and receivers in the PHY:
FS and LS transceivers. These are the legacy USB1.x transceivers.
HS transceivers
To bias the transistors and run the logic, the PHY also contains reference generation circuitry which
consists of:
A digital phase-locked loop (DPLL) that does a frequency multiplication to achieve the 480-MHz
low-jitter lock necessary for USB, and the clock required for the switched capacitor resistance block
A switched capacitor resistance block that replicates an external resistor on chip
Built-in pullup and pulldown resistors are used as part of the protocol signaling.
The PHY also contains circuitry that protects it from an accidental 5-V short on the DP and DM lines and
from 8-kV IEC ESD strikes.
When the voltage on DP or DM exceeds 3.6 V, a stress condition is detected. In this case, the current is
drawn from the DP/DM line, to prevent damage caused by the stress voltage. In this condition, the
VRUSB_3V supply can be charged as high as 3.6 V. Table 7-6 lists the tolerances.
USB HS 2.0 OTG Transceiver
106
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