參數(shù)資料
型號： TPS65950ZXNR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA209
封裝： 7 X 7 MM, 0.40 MM PITCH, PLASTIC, BGA-209
文件頁數(shù)： 5/167頁
文件大?。?/td> 2566K
代理商： TPS65950ZXNR
ULPI
DATA0:UART_TX
DATA1:UART_RX
DATA2:UART_RTS
DATA3:UART_CTS
Device
MCPC connector
DP/RXD/MIC_R
DM/TXD/SPKR_L
RTSO
CTSI
032-050
TPS65950
Integrated Power Management/Audio Codec
SWCS032 – OCTOBER 2008
www.ti.com
Audio (mono/stereo) signaling: In this mode, the ULPI data bus is redefined as a 4-pin UART interface,
which exchanges data through a direct access to the FS/LS analog transmitter and receiver.
The UART data are sent and received on the USB D+/D– pads, and the handshake signals are sent and
received on the RTSO/CTSI pads.
Figure 7-3 shows the MCPC UART and handshake mode data flow.
Figure 7-3. MCPC UART and Handshake Mode Data Flow
Table 7-1 lists the McPC UART and handshake mode timings.
Table 7-1. MCPC UART and Handshake Mode Timings
Notation
Parameter
Min(1)
Max(2)
Unit
CK5
td(UART_TXH-DM)
Delay time, UART_TX rising edge to DM transition
10
37
ns
CK6
td(UART_TXL-DM)
Delay time, UART_TX falling edge to DM transition
2.5
13
ns
CK7
td(DPH-UART_RX)
Delay time, DP rising edge to UART_RX transition
17
40
ns
CK8
td(DPL-UART_RX)
Delay time, DP falling edge to UART_RX transition
26
50
ns
CK9
td(UART_CTSH-RTSO)
Delay time, UART_CTS rising edge to RTSO transition
1
18
ns
CK10
td(UART_CTSL-RTSO)
Delay time, UART_CTS falling edge to RTSO transition
1
18
ns
CK11
td(CTSIH-UART_RTS)
Delay time, CTSI rising edge to UART_RTS transition
3
16
ns
CK12
td(CTSIL-UART_RTS)
Delay time, CTSI falling edge to UART_RTS transition
3
16
ns
(1)
Min = Minimum value
(2)
Max = Maximum value
USB HS 2.0 OTG Transceiver
102
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