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VOLTAGE REFERENCE
OSCILLATOR AND PWM RAMP
Switching Frequency +
100 kW
R
500 [kHz]
(5)
ERROR AMPLIFIER
DEAD-TIME CONTROL AND MOSFET
PWM CONTROL
TPS54974
SLVS458B – JANUARY 2003 – REVISED FEBRUARY 2005
VBIAS of 2.7 V, and external loads on VBIAS with ac
error amplifier output voltage, the PWM comparator
or digital switching noise may degrade performance.
resets the latch, thus turning off the high-side FET
The VBIAS pin may be useful as a reference voltage
and turning on the low-side FET. The low-side FET
for external circuits. VBIAS is derived from the VIN
remains on until the next oscillator pulse discharges
pin (see the internal block diagram).
the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or
above the PWM peak voltage. If the error amplifier is
The voltage reference system produces a precise Vref
high, the PWM latch is never reset, and the high-side
signal by scaling the output of a temperature-stable
FET remains on until the oscillator pulse signals the
bandgap circuit. During manufacture, the bandgap
control logic to turn the high-side FET off and the
and scaling circuits are trimmed to produce 0.891 V
low-side FET on. The device operates at its maxi-
at the output of the error amplifier, with the amplifier
mum duty cycle until the output voltage rises to the
connected as a voltage follower. The trim procedure
regulation set-point, setting VSENSE to approxi-
adds
to
the
high-precision
regulation
of
the
mately the same voltage as VREF. If the error
TPS54974, because it cancels offset errors in the
amplifier output is low, the PWM latch is continually
scale and error amplifier circuits.
reset and the high-side FET does not turn on. The
low-side FET remains on until the VSENSE voltage
decreases
to
a
range
that
allows
the
PWM
The oscillator frequency is set to an internally fixed
comparator to change states. The TPS54974 is
value of 350 kHz. The oscillator frequency can be
capable of sinking current continuously until the
externally adjusted from 280 to 700 kHz by con-
output reaches the regulation set-point.
necting a resistor between the RT pin to ground. The
If the current limit comparator trips for longer than
switching frequency is approximated by the following
100 ns, the PWM latch resets before the PWM ramp
equation, where R is the resistance from RT to
exceeds the error amplifier output. The high-side FET
AGND:
turns off and low-side FET turns on to decrease the
energy in the output inductor and consequently the
output current. This process is repeated each cycle in
which the current limit comparator is tripped.
The high-performance, wide bandwidth, voltage error
amplifier sets the TPS54974 apart from most dc/dc
DRIVERS
converters. The user is given the flexibility to use a
Adaptive dead-time control prevents shoot-through
wide range of output L and C filter components to suit
current
from
flowing
in
both
N-channel
power
the particular application needs. Type-2 or Type-3
MOSFETs during the switching transitions by actively
compensation can be employed using external com-
controlling the turnon times of the MOSFET drivers.
pensation components.
The high-side driver does not turn on until the voltage
at the gate of the low-side FET is below 2 V. While
the low-side driver does not turn on until the voltage
at the gate of the high-side MOSFET is below 2 V.
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
The high-side and low-side drivers are designed with
logic. Referring to the internal block diagram, the
300-mA source and sink capability to quickly drive the
control logic includes the PWM comparator, OR gate,
power MOSFETs gates. The low-side driver is sup-
PWM latch, and portions of the adaptive dead-time
plied from VIN, while the high-side drive is supplied
and control-logic block. During steady-state operation
from the BOOT pin. A bootstrap circuit uses an
below
the
current
limit
threshold,
the
PWM
external BOOT capacitor and an internal 2.5-
comparator output and oscillator pulse train alter-
bootstrap switch connected between the VIN and
nately reset and set the PWM latch. Once the PWM
BOOT pins. The integrated bootstrap switch improves
latch is set, the low-side FET remains on for a
drive efficiency and reduces external component
minimum duration set by the oscillator pulse width.
count.
During this period, the PWM ramp discharges rapidly
to its valley voltage. When the ramp begins to charge
back up, the low-side FET turns off and high-side
FET turns on. As the PWM ramp voltage exceeds the
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