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參數(shù)資料
| 型號(hào)： | TPS5211 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH FREQUENCY PROGRAMMABLE HYSTERETIC REGULATOR CONTROLLER |
| 中文描述： | 可編程滯高頻穩(wěn)壓控制器 |
| 文件頁數(shù)： | 4/32頁 |
| 文件大?。?/td> | 469K |
| 代理商： | TPS5211 |
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TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER
SLVS243 – SEPTEMBER 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description
V
REF
The reference/voltage identification (VID) section consists of a temperature-compensated bandgap reference
and a 5-bit voltage selection network. The 5 VID terminals are inputs to the VID selection network and are
TTL-compatible inputs internally pulled up to 5 V by a resistor divider connected to V
CC
. The VID codes conform
to the Intel VRM 8.3 DC-DC Converter Specificationfor voltage settings between 1.8 V and 3.5 V, and they are
decremented by 50 mV, down to 1.3 V, for the lower VID settings. Voltages higher than V
REF
can be implemented
using an external divider. Refer to Table 1 for the VID code settings. The output voltage of the VID network, V
REF
,
is within
±
1.5% of the nominal setting over the VID range of 1.3 V to 25 V, including a junction temperature range
of 5
°
C to +125
°
C, and a V
CC
supply voltage range of 11.4 V to 12.6 V. The output of the reference/VID network
is indirectly brought out through a buffer to the V
REFB
pin. The voltage on this pin will be within 5mV of V
REF
.
It is not recommended to drive loads with V
REFB
, other than setting the hysteresis of the hysteretic comparator,
because the current drawn from V
REFB
sets the charging current for the slowstart capacitor. Refer to the
slowstart section for additional information.
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by 2 external resistors and is centered on V
REF
. The 2 external resistors form a resistor divider from V
REFB
to ANAGND, with the output voltage connecting to the VHYST pin. The hysteresis of the comparator will be
equal to twice the voltage differencebetween the VREFB and VHYST pins. The propagation delay from the
comparator inputs to the driver outputs is 250 ns (maximum). The maximum hysteresis setting is 60 mV.
low-side driver
The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The bias to the low-side driver is internally connected to the DRV regulator.
high-side driver
The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The high-side driver can be configured either as a ground-referenced driver or as a floating
bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV
regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved
drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver
can be referenced to ground by connecting BOOTLO to DRVGND, and connecting BOOT to either DRV or V
CC
.
The rms current through the drivers output should not exceed 110 mA. Refer to the application information
section to determine how to calculate an operating frequency to meet this requirement.
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed
to turn on until the gate-drive voltage to the low-side FETs is below 2 V; the low-side driver is not allowed to turn
on until the voltage at the junction of the high-side and low-side FETs (Vphase) is below 2 V.
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