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參數(shù)資料
| 型號： | TPS3600x33PWR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | BATTERY-BACKUP SUPERVISORS FOR LOW-POWER PROCESSORS |
| 中文描述： | 電池備份監(jiān)事的低功耗處理器 |
| 文件頁數(shù)： | 13/26頁 |
| 文件大?。?/td> | 510K |
| 代理商： | TPS3600X33PWR |
SLVS336B DECEMBER 2000 REVISED JANUARY 2007
13
timing requirements at R
L
= 1 M
, C
L
= 50 pF, T
A
= 40
°
C to 85
°
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
μ
s
VDD
MR
WDI
VIH = VIT + 0.2 V, VIL = VIT 0.2 V
5
1
tw
Pulse width
VDD > VIT + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD
100
ns
switching characteristics at R
L
= 1 M
, C
L
= 50 pF, T
A
= 40
°
C to 85
°
C
PARAMETER
TEST CONDITIONS
VDD
≥
VIT + 0.2 V,
MR
≥
0.7 x VDD,
See timing diagram
MIN
TYP
MAX
UNIT
td
Delay time
60
100
140
ms
t(tout)
Watchdog time-out
VDD > VIT + 0.2 V,
See timing diagram
0.48
0.8
1.12
s
tPLH
Propagation (delay) time,
low-to-high-level output
50% RESET to 50% CEOUT
VOUT = VIT
15
μ
s
VDD to RESET
VIL = VIT 0.2 V,
VIH = VIT + 0.2 V
VIL = V(PFI) 0.2 V,
VIH = V(PFI) + 0.2 V
VDD
≥
VIT + 0.2 V,
VIL = 0.3 x VDD,
VIH = 0.7 x VDD
VDD = 1.8 V
VDD = 3.3 V
VDD = 5 V
VIL = VBAT 0.2 V,
VIH = VBAT + 0.2 V,
V(BAT) < VIT
2
5
μ
s
PFI to PFO
3
5
μ
s
tPHL
Propagation (delay) time,
high-to-low-level output
MR to RESET
0.1
1
μ
s
50% CEIN to 50% CEOUT
CL = 50 pF only (see Note 6)
5
15
ns
1.6
5
ns
1
3
ns
Transition time
VDD to BATTON
3
μ
s
NOTE 6: Ensured by design.
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
5
Static Drain-source on-state resistance VDD to VOUT
Static Drain-source on-state resistance VBAT to VOUT
Static Drain-source on-state resistance
vs Output current
rDS(on)
6
vs Chip enable input voltage
7
IDD
VIT
Supply current
vs Supply voltage
8, 9
Normalized threshold voltage
vs Free-air temperature
10
High-level output voltage at RESET
11, 12
VOH
High-level output voltage at PFO
vs High-level output current
13, 14
High-level output voltage at CEOUT
15, 16, 17, 18
Low-level output voltage at RESET
19, 20
VOL
Low-level output voltage at CEOUT
vs Low-level output current
21, 22
Low-level output voltage at BATTON
Minimum Pulse Duration at VDD
Minimum Pulse Duration at PFI
23, 24
25
tp(min)
vs Threshold voltage overdrive at VDD
vs Threshold voltage overdrive at PFI
26
www.ti.com
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| TPS3606-33DGS | 功能描述:監(jiān)控電路 Battery-Backup for LP Processor RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TPS3606-33DGSG4 | 功能描述:監(jiān)控電路 Battery-Backup for LP Processor RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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