參數(shù)資料
型號： TPS2301PW
廠商： Texas Instruments, Inc.
英文描述： DUAL HOT SWAP POWER CONTROLLER WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
中文描述： 雙熱插拔電源與獨立斷路器及功率控制器，高質量的報告
文件頁數(shù)： 6/22頁
文件大?。?/td> 422K
代理商： TPS2301PW
TPS2300, TPS2301
DUAL HOT SWAP POWER CONTROLLER WITH INDEPENDENT
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265B – FEBRUARY 2000 – REVISED APRIL 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating temperature range (–40
°
C < T
A
< 85
°
C),
3 V
≤
V
I(IN1)
≤
13 V, 3 V
≤
V
I(IN2)
≤
5.5 V ( unless otherwise noted) (continued)
TIMER
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOT(TIMER)
Threshold voltage, TIMER
0.4
0.5
0.6
V
μ
A
mA
Charge current, TIMER
VI(TIMER) = 0 V
VI(TIMER) = 1 V
35
50
65
Discharge current, TIMER
1
2.5
circuit breaker
PARAMETER
TEST CONDITIONS
RISETx = 1 k
MIN
TYP
MAX
UNIT
VIT(CB)
IIB(ISENSEx)
Undervoltage voltage, circuit breaker
40
50
60
mV
μ
A
Input bias current, ISENSEx
0.1
5
Discharge current GATEx
Discharge current, GATEx
VO(GATEx) = 4 V
VO(GATEx) = 1 V
Cg = 50 pF,
(50% to 10%)
400
25
800
150
mA
tpd(CB)
Propagation (delay) time, comparator inputs to
gate output
10 mV overdrive,
CO(timer) = 50 pF
1.3
μ
s
ENABLE, active low (TPS2300)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH(ENABLE)
VIL(ENABLE)
High-level input voltage, ENABLE
2
V
Low-level input voltage, ENABLE
0.8
V
RI(ENABLE)
Input pullup resistance,
ENABLE
See Note 3
100
200
300
k
td_off(ENABLE)
Turnoff delay time, ENABLE
VI(ENABLE) ncreasing above stop threshold; 100
ns rise time, 20 mV overdrive (see Note 2)
60
μ
s
td_on(ENABLE)
Turnon delay time, ENABLE
VI(ENABLE) decreasing below start threshold;
100 ns fall time, 20 mV overdrive (see Note 2)
125
μ
s
NOTES:
2. Specified, but not production tested.
3. Test IO of ENABLE at VI(ENABLE) = 1 V and 0 V, then RI(ENABLE) =
1 V
IO_0V
IO_1V
ENABLE, active high (TPS2301)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH(ENABLE)
VIL(ENABLE)
High-level input voltage, ENABLE
2
V
Low-level input voltage, ENABLE
0.7
V
RI(ENABLE)
Input pulldown resistance,
ENABLE
100
150
300
k
td_on(ENABLE)
Turnon delay time, ENABLE
VI(ENABLE) increasing above start threshold;
100 ns rise time, 20 mV overdrive (see Note 2)
85
μ
s
td_off(ENABLE)
Turnoff delay time, ENABLE
VI(ENABLE) decreasing below stop threshold;
100 ns fall time, 20 mV overdrive (see Note 2)
100
μ
s
NOTE 2: Specified, but not production tested.
PREREG
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VREG
PREREG output voltage
4.5
≤
VI(IN1)
≤
13 V
VI(IN1) = 3 V
3.5
4.1
5.5
V
Vdrop_PREREG
PREREG dropout voltage
0.1
V
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