參數(shù)資料
型號： TPS2301PW
廠商： Texas Instruments, Inc.
英文描述： DUAL HOT SWAP POWER CONTROLLER WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
中文描述： 雙熱插拔電源與獨立斷路器及功率控制器，高質(zhì)量的報告
文件頁數(shù)： 5/22頁
文件大?。?/td> 422K
代理商： TPS2301PW
TPS2300, TPS2301
DUAL HOT SWAP POWER CONTROLLER WITH INDEPENDENT
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265B – FEBRUARY 2000 – REVISED APRIL 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating temperature range (–40
°
C < T
A
< 85
°
C),
3 V
≤
V
I(IN1)
≤
13 V, 3 V
≤
V
I(IN2)
≤
5.5 V (unless otherwise noted)
general
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
II(IN1)
II(IN2)
Input current, IN1
VI(ENABLE) = 5 V (TPS2301),
VI(ENABLE) = 0 V (TPS2300)
VI(ENABLE) = 0 V (TPS2301)
VI(ENABLE) = 5 V (TPS2300)
0.5
1
mA
μ
A
Input current, IN2
75
200
II(stby)
Standby current (sum of currents into IN1, IN2,
ISENSE1, ISENSE2, ISET1, and ISET2)
5
μ
A
GATE1
PARAMETER
TEST CONDITIONS
MIN
TYP
11.5
MAX
UNIT
VG(GATE1_3V)
VG(GATE1_4.5V)
VG(GATE1_10.8V)
II(GATE1) = 500 nA,
DISCH1 open
DISCH1 o en
VI(IN1) = 3 V
VI(IN1) = 4.5 V
VI(IN1) = 10.8 V
9
Gate voltage
10.5
14.5
V
16.8
21
VC(GATE1)
Clamping voltage, GATE1
to DISCH1
9
10
12
V
IS(GATE1)
Source current, GATE1
3 V
≤
VI(IN1)
≤
13.2 V, 3 V
≤
VO(VREG)
≤
5.5 V,
VI(GATE1) = VI(IN1) + 6 V
3 V
≤
VI(IN1)
≤
13.2 V, 3 V
≤
VO(VREG)
≤
5.5 V,
VI(GATE1) = VI(IN1)
10
14
20
μ
A
Sink current, GATE1
50
75
100
μ
A
VI(IN1) = 3 V
VI(IN1) = 4.5 V
VI(IN1) = 10.8 V
VI(IN1) = 3 V
VI(IN1) = 4.5 V
VI(IN1) = 10.8 V
0.5
tr(GATE1)
Rise time, GATE1
Cg to GND = 1 nF (see Note 2)
0.6
ms
1
0.1
tf(GATE1)
Fall time, GATE1
Cg to GND = 1 nF (see Note 2)
0.12
0.2
ms
GATE2
PARAMETER
TEST CONDITIONS
MIN
TYP
11.7
MAX
UNIT
VG(GATE2_3V)
VG(GATE2_4.5V)
Gate voltage
II(GATE2)= 500 nA DISCH2 open
II(GATE2) = 500 nA, DISCH2 o en
VI(IN2) = 3 V
VI(IN2) = 4.5 V
9
V
10.5
14.7
VC(GATE2)
Clamping voltage,
GATE2 to DISCH2
9
10
12
V
IS(GATE2)
Source current,
GATE2
3 V
≤
VI(IN2)
≤
5.5 V, 3 V
≤
VO(VREG)
≤
5.5 V,
VI(GATE2) = VI(IN2) + 6 V
3 V
≤
VI(IN2)
≤
5.5 V, 3 V
≤
VO(VREG)
≤
5.5 V,
VI(GATE2) = VI(IN2)
VI(IN2) = 3 V
(see Note 2)
VI(IN2) = 4.5 V
Cg to GND = 1 nF
(see Note 2)
VI(IN2) = 4.5 V
10
14
20
μ
A
Sink current, GATE2
50
75
100
μ
A
t(GATE2)
tr(GATE2)
Rise time GATE2
Rise time, GATE2
Cg to GND = 1 nF
0.5
ms
VO(VREG)= 3 V
VO(VREG) = 3 V
0.6
tf(GATE2)
Fall time GATE2
Fall time, GATE2
VI(IN2) = 3 V
0.1
0.12
ms
NOTE 2: Specified, but not production tested.
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