參數(shù)資料
型號(hào)： TP28F010-150
廠商： INTEL CORP
元件分類(lèi)： DRAM
英文描述： 28F010 1024K (128K X 8) CMOS FLASH MEMORY
中文描述： 128K X 8 FLASH 12V PROM, 150 ns, PDIP32
封裝： 0.620 X 1.640 INCH, PLASTIC, DIP-32
文件頁(yè)數(shù)： 6/33頁(yè)
文件大?。?/td> 895K
代理商： TP28F010-150
28F010
E
6
290207-1
Figure 1. 28F010 Block Diagram
Table 1. Pin Description
Symbol
Type
Name and Function
A
0
–A
16
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally
latched during a write cycle.
DQ
0
–DQ
7
INPUT/OUTPUT
DATA INPUT/OUTPUT:
Inputs data during memory write cycles; outputs
data during memory read cycles. The data pins are active high and float to
tri-state
off
when the chip is deselected or the outputs are disabled. Data is
internally latched during a write cycle
CE#
INPUT
CHIP ENABLE:
Activates the device's control logic, input buffers, decoders
and sense amplifiers. CE# is active low; CE# high deselects the memory
device and reduces power consumption to standby levels.
OE#
INPUT
OUTPUT ENABLE:
Gates the devices output through the data buffers
during a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE:
Controls writes to the control register and the array. Write
enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edge of the WE# pulse.
Note:
With V
PP
≤
6.5 V, memory contents cannot be altered.
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