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參數(shù)資料
| 型號(hào)： | TP28F010-150 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 28F010 1024K (128K X 8) CMOS FLASH MEMORY |
| 中文描述： | 128K X 8 FLASH 12V PROM, 150 ns, PDIP32 |
| 封裝： | 0.620 X 1.640 INCH, PLASTIC, DIP-32 |
| 文件頁(yè)數(shù)： | 10/33頁(yè) |
| 文件大?。?/td> | 895K |
| 代理商： | TP28F010-150 |
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28F010
E
10
2.2.1.3
Standby
With CE# at a logic-high level, the standby
operation disables most of the 28F010’s circuitry
and
substantially
reduces
consumption. The outputs are placed in a high-
impedance state, independent of the OE# signal. If
the
28F010
is
deselected
programming, or program/erase verification, the
device draws active current until the operation is
terminated.
device
power
during
erasure,
2.2.1.4
Intelligent Identifier Operation
The intelligent identifier operation outputs the
manufacturer code (89H) and device code (B4H).
Programming equipment automatically matches the
device with its proper erase and programming
algorithms.
With CE# and OE# at a logic low level, raising A
9
to
high voltage V
ID
(see
DC Characteristics
) activates
the operation. Data read from locations 0000H and
0001H represent the manufacturer's code and the
device code, respectively.
The manufacturer and device codes can also be
read via the command register, for instances where
the 28F010 is erased and reprogrammed in the
target system. Following a write of 90H to the
command register, a read from address location
0000H outputs the manufacturer code (89H). A
read from address 0001H outputs the device code
(B4H).
2.2.1.5
Write
Device erasure and programming are accomplished
via the command register, when high voltage is
applied to the V
PP
pin. The contents of the register
serve as input to the internal state machine. The
state machine outputs dictate the function of the
device.
The command register itself does not occupy an
addressable memory location. The register is a
latch used to store the command, along with
address and data information needed to execute
the command.
The command register is written by bringing WE# to
a logic-low level (V
IL
), while CE# is low. Addresses
are latched on the falling edge of WE#, while data is
latched on the rising edge of the WE# pulse.
Standard microprocessor write timings are used.
Refer to
AC Characteristics
—Write/Erase/Program
Only Operations
and the erase/programming
waveforms for specific timing parameters.
2.2.2
COMMAND DEFINITIONS
When low voltage is applied to the V
PP
pin, the
contents of the command register default to 00H,
enabling read-only operations.
Placing high voltage on the V
PP
pin enables
read/write operations. Device operations are
selected by writing specific data patterns into the
command register. Table 3 defines these 28F010
register commands.
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