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參數(shù)資料
| 型號： | TP13057A |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | Combination Codec/Filter(單片，串行接口，組合脈沖編碼譯碼器和濾波器，增強降噪) |
| 中文描述： | 組合編解碼器/濾波器（單片，串行接口，組合脈沖編碼譯碼器和濾波器，增強降噪） |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 361K |
| 代理商： | TP13057A |
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
asynchronous operation
For asynchronous operation, separate transmit and receive clocks can be applied. MCLKX and MCLKR must
be 2.048 MHz for the TP3057A and TP13057A, 1.536 MHz or 1.544 MHz for the TP3054A and TP13054A and
need not be synchronous. However, for best performance, MCLKR should be synchronous with MCLKX. This
is easily achieved by applying only static logic levels to MCLKR/PDN. This connects MCLKX to all internal
MCLKR functions. For 1.544-MHz operation, the device compensates for the 193rd clock pulse of each frame.
Each encoding cycle is started with FSX and FSX must be synchronous with MCLKX and BCLKX. Each
decoding cycle is started with FSR and FSR must be synchronous with BCLKR. The logic levels shown in
Table 1 are not valid in the asynchronous mode. BCLKX and BCLKR can operate from 64 kHz to 2.048 MHz.
short-frame sync operation
The device can operate with either a short- or a long-frame sync pulse. On power up, the device automatically
goes into the short-frame mode where both FSX and FSR must be one bit-clock period long with timing
relationships specified in Figure 1. With FSX high during a falling edge of BCLKX, the next rising edge of BCLKX
enables the 3-state output buffer, DX, which outputs the sign bit. The remaining seven bits are clocked out on
the following seven rising edges, and the next falling edge disables DX. With FSR high during a falling edge
of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following
seven falling edges latch in the seven remaining bits. The short-frame sync pulse may be utilized in either the
synchronous or asynchronous mode.
long-frame sync operation
Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing
relationships as shown in Figure 2. Using the transmit frame sync (FSX), the device detects whether a short-
or long-frame sync pulse is being used. For 64-kHz operation, the frame-sync pulse must be kept low for a
minimum of 160 ns. The rising edge of FSX or BCLKX, whichever occurs later, enables the DX 3-state output
buffer. The first bit clocked out is the sign bit. The next seven rising edges of BCLKX edges clock out the
remaining seven bits. The falling edge of BCLKX following the eighth rising edge or FSX going low, whichever
occurs later, disables DX. A rising edge on FSR, the receive-frame sync pulse, causes the PCM data at DR to
be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). The long-frame sync
pulse can be utilized in either the synchronous or asynchronous mode.
transmit section
The transmit section input is an operational amplifier with provision for gain adjustment using two external
resistors. The low noise and wide bandwidth characteristics of these devices provide gains in excess of 20 dB
across the audio passband. The operational amplifier drives a unity-gain filter consisting of an RC active prefilter
followed by an eighth-order switched-capacitor band-pass filter clocked at 256 kHz. The output of this filter
directly drives the encoder sample-and-hold circuit. As per
μ
-law (TP3054A and TP13054A) or A-law (TP3057A
and TP13057A) coding conventions, the ADC is a companding type. A precision voltage reference provides a
nominal input overload (t
[max]
) of nominally 2.5 V peak. The sampling of the filter output is controlled by the FSX
frame-sync pulse. Then the successive-approximation encoding cycle begins. The 8-bit code is loaded into a
buffer and shifted out through DX at the next FSX pulse. The total encoding delay is approximately 290
μ
s. Any
offset voltage due to the filters or comparator is cancelled by sign-bit integration.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TP3057A | Combination Codec/Filter(單片，串行接口，組合脈沖編碼譯碼器和濾波器,單端接收輸出，增強降噪) |
| TP13054A | Combination Codec/Filter(單片，串行接口，組合脈沖編碼譯碼器和濾波器) |
| TP13067AN | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3067ADW | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP13067ADW | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP13057ADW | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13057ADWR | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13057AJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law CODEC |
| TP13057AN | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13057B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
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