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參數(shù)資料
| 型號(hào)： | TP13057A |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | Combination Codec/Filter(單片，串行接口，組合脈沖編碼譯碼器和濾波器，增強(qiáng)降噪) |
| 中文描述： | 組合編解碼器/濾波器（單片，串行接口，組合脈沖編碼譯碼器和濾波器，增強(qiáng)降噪） |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大小： | 361K |
| 代理商： | TP13057A |
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TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
VCC
DGND
VBB
Figure 3. Latch-Up Protection Diode Connection
internal sequencing
Power-on reset circuitry initializes the TP3054A, TP3057A, TP13054A, and TP13057A devices when power
is first applied, placing it into the power-down mode. DX and VFRO outputs go into high-impedance states and
all nonessential circuitry is disabled. A low level or clock applied to MCLKR/PDN powers up the device and
activates all circuits. DX, a 3-state PCM data output, remains in the high-impedance state until the arrival of the
second FSX pulse.
synchronous operation
For synchronous operation, a clock is applied to MCLKX. MCLKR/PDN is used as a power-down control. A low
level on MCLKR powers up the device and a high level powers it down. In either case, MCLKX is selected as
the master clock for both receive and transmit direction. BCLKX must also have a bit clock applied to it. The
selection of the proper internal divider for a master-clock frequency of 1.536 MHz, 1.544 MHz, or 2.048 MHz
can be done via BCLKR/CLKSEL. The device automatically compensates for the 193rd clock pulse of each
frame.
A fixed level on BCLKR/CLKSEL selects BCLKX as the bit clock for both the transmit and receive directions.
Table 1 indicates the frequencies of operation that can be selected depending on the state of BCLKR/CLKSEL.
In the synchronous mode, BCLKX may be in the range from 64 kHz to 2.048 MHz but must be synchronous
with MCLKX.
Table 1. Selection of Master-Clock Frequencies
BCLKR/CLKSEL
MASTER-CLOCK FREQUENCY SELECTED
TP13054A, TP3054A
TP13057A, TP3057A
Clock Input
1.536 MHz or 1.544 MHz
2.048 MHz
Logic Input L
(sync mode only)
2.048 MHz
1.536 MHz or 1.544 MHz
Logic Input H (open)
(sync mode only)
1.536 MHz or 1.544 MHz
2.048 MHz
The encoding cycle begins with each FSX pulse and the PCM data from the previous cycle is shifted out of the
enabled DX output on the rising edge of BCLKX. After eight bit-clock periods, the 3-state DX output is returned
to the high-impedance state. With an FSR pulse, PCM data is latched via DR on the falling edge of BCLKX (or
BCLKR, if running). FSX and FSR must be synchronous with MCLKX and MCLKR.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TP3057A | Combination Codec/Filter(單片，串行接口，組合脈沖編碼譯碼器和濾波器,單端接收輸出，增強(qiáng)降噪) |
| TP13054A | Combination Codec/Filter(單片，串行接口，組合脈沖編碼譯碼器和濾波器) |
| TP13067AN | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3067ADW | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP13067ADW | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP13057ADW | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13057ADWR | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13057AJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law CODEC |
| TP13057AN | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13057B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
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