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參數(shù)資料
| 型號： | TN28F020-90 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 28F020 2048K (256K X 8) CMOS FLASH MEMORY |
| 中文描述： | 256K X 8 FLASH 12V PROM, 90 ns, PQCC32 |
| 封裝： | 0.450 X 0.550 INCH, PLASTIC, LCC-32 |
| 文件頁數(shù)： | 11/38頁 |
| 文件大?。?/td> | 878K |
| 代理商： | TN28F020-90 |
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E
28F020
11
Table 3. Command Definitions
Command
Bus
Cycles
Req’d
First Bus Cycle
Second Bus Cycle
Operation
(1)
Address
(2)
Data
(3)
Operation
(1)
Address
(2)
Data
(3)
Read Memory
1
Write
X
00H
Read Intelligent
Identifier Codes
(4)
3
Write
IA
90H
Read
IA
ID
Set-Up
Erase/Erase
(5)
2
Write
X
20H
Write
X
20H
Erase Verify
(5)
2
Write
EA
A0H
Read
X
EVD
Set-Up Program/
Program
(6)
2
Write
X
40H
Write
PA
PD
Program Verify
(6)
2
Write
X
C0H
Read
X
PVD
Reset
(7)
2
Write
X
FFH
Write
X
FFH
NOTES:
1.
2.
Bus operations are defined in Table 2.
IA = Identifier address: 00H for manufacturer code, 01H for device code.
EA = Erase Address: Address of memory location to be read during erase verify.
PA = Program Address: Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
ID = Identifier Address: Data read from location IA during device identification (Mfr = 89H, Device = BDH).
EVD = Erase Verify Data: Data read from location EA during erase verify.
PD = Program Data: Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD = Program Verify Data: Data read from location PA during program verify. PA is latched on the Program command.
Following the Read Intelligent ID command, two read operations access manufacturer and device codes.
Figure 5 illustrates the 28F020 Quick-Erase Algorithmflowchart.
Figure 4 illustrates the 28F020 Quick-Pulse Programming Algorithmflowchart.
The second bus cycle must be followed by the desired command register write.
3.
4.
5.
6.
7.
2.2.2.1
Read Command
While V
PP
is high, for erasure and programming,
memory contents can be accessed via the Read
command. The read operation is initiated by writing
00H into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register
contents are altered.
The default contents of the register upon V
PP
power-up is 00H. This default value ensures that
no spurious alteration of memory contents occurs
during the V
PP
power transition. Where the V
PP
supply is hardwired to the 28F020, the device
powers-up and remains enabled for reads until the
command register contents are changed. Refer to
the AC Characteristics
—
Read-Only Operations
and waveforms for specific timing parameters.
2.2.2.2
Intelligent Identifier Command
Flash
applications where the local CPU alters memory
contents. As such, manufacturer and device codes
must be accessible while the device resides in the
target system. PROM programmers typically
access signature codes by raising A
9
to a high
voltage. However, multiplexing high voltage onto
address lines is not a desired system design
practice.
memories
are
intended
for
use
in
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