參數(shù)資料
型號： TMX320F28044ZGMS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processor
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 60/107頁
文件大?。?/td> 784K
代理商： TMX320F28044ZGMS
www.ti.com
4.8
Inter-Integrated Circuit (I
2
C)
TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
The F28044 device contains one I
2
C Serial Port. Figure 4-15 shows how the I
2
C peripheral module
interfaces within the F28044 device.
The I
2
C module has the following features:
Compliance with the Philips Semiconductors I
2
C-bus specification (version 2.1):
–
Support for 1-bit to 8-bit format transfers
–
7-bit and 10-bit addressing modes
–
General call
–
START byte mode
–
Support for multiple master-transmitters and slave-receivers
–
Support for multiple slave-transmitters and master-receivers
–
Combined master transmit/receive and receive/transmit mode
–
Data transfer rate of from 10 kbps up to 400 kbps (Philips Fast-mode rate)
One 16-bit receive FIFO and one 16-bit transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
–
Transmit-data ready
–
Receive-data ready
–
Register-access ready
–
No-acknowledgment received
–
Arbitration lost
–
Stop condition detected
–
Addressed as slave
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable/disable capability
Free data format mode
Peripherals
60
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