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參數(shù)資料
| 型號： | TMS6648148 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 4 194 304 4位/ 2 097 152 8位/ 1 048 576由16位4，銀行同步動(dòng)態(tài)隨機(jī)存取記憶體 |
| 文件頁數(shù)： | 4/56頁 |
| 文件大?。?/td> | 958K |
| 代理商： | TMS6648148 |
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TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
device numbering conventions (SDRAM family nomenclature)
xx
6
4 –xx
Product Family:
6 =
Density, Refresh, Interface:
64 =
64M
Organization/Special Architecture:
41 =
x 4 Pipeline
81 =
x 8 Pipeline
16 =
x 16 Pipeline
Number of Banks:
4 =
Four Banks
Speed:
8 tCK3
=
8 ns
8A tCK3
=
8 ns
10 tCK3
=
10 ns
Synchronous Dynamic Random-Access Memory
4K Auto-Refresh LVTTL
TMS
64
Prefix:
TMS = Commercial / MOS
operation
All inputs to the ’664xx4 SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs
(DQ0–DQ3 for x4, DQ0–DQ7 for x8, and DQ0–DQ15 for x16) are also referenced to the rising edge of CLK.
The ’664xx4 has four banks that are accessed independently. A bank must be activated before it can be
accessed (read from or written to). Refresh cycles refresh all banks alternately.
Five basic commands or functions control most operations of the ’664xx4:
Bank activate/row-address entry
Column-address entry/write operation
Column-address entry/read operation
Bank deactivate
Auto-refresh/self-refresh entry
Additionally, operations can be controlled by three methods: using chip select (CS) to select/deselect the
devices, using DQMx to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend (or
gate) the CLK input. The device contains a mode register that must be programmed for proper operation.
Table 1 through Table 3 show the various operations that are available on the ’664xx4. These truth tables
identify the command and/or operations and their respective mnemonics. Each truth table is followed by a
legend that explains the abbreviated symbols. An access operation refers to any READ (READ-P) or WRT
(WRT-P) command in progress at cycle n. Access operations include the cycle upon which the READ (READ-P)
or WRT (WRT-P) command is entered and all subsequent cycles through the completion of the access burst.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMS6648148A | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS6641648 | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS6641648A | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS66441410 | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS6644148 | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS6648148A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS664814DGE-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X2MX8|CMOS|TSOP|54PIN|PLASTIC |
| TMS664814DGE-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X2MX8|CMOS|TSOP|54PIN|PLASTIC |
| TMS664814DGE-8A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X2MX8|CMOS|TSOP|54PIN|PLASTIC |
| TMS6708-20DJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
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