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| 型號： | TMS6644148A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 4 194 304 4位/ 2 097 152 8位/ 1 048 576由16位4，銀行同步動態(tài)隨機(jī)存取記憶體 |
| 文件頁數(shù)： | 10/56頁 |
| 文件大小： | 958K |
| 代理商： | TMS6644148A |
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TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
10
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
burst sequence (continued)
Table 6. 8-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A2–A0
DECIMAL
4TH
3
BINARY
4TH
011
START
0
2ND
1
3RD
2
5TH
4
6TH
5
7TH
6
8TH
7
START
000
2ND
001
3RD
010
5TH
100
6TH
101
7TH
110
8TH
111
1
2
3
4
5
6
7
0
001
010
011
100
101
110
111
000
2
3
4
5
6
7
0
1
010
011
100
101
110
111
000
001
Serial
3
4
5
6
7
0
1
2
011
100
101
110
111
000
001
010
4
5
6
7
0
1
2
3
100
101
110
111
000
001
010
011
5
6
7
0
1
2
3
4
101
110
111
000
001
010
011
100
6
7
0
1
2
3
4
5
110
111
000
001
010
011
100
101
7
0
1
2
3
4
5
6
111
000
001
010
011
100
101
110
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
1
0
3
2
5
4
7
6
001
000
011
010
101
100
111
110
2
3
0
1
6
7
4
5
010
011
000
001
110
111
100
101
Interleave
3
2
1
0
7
6
5
4
011
010
001
000
111
110
101
100
4
5
6
7
0
1
2
3
100
101
110
111
000
001
010
011
5
4
7
6
1
0
3
2
101
100
111
110
001
000
011
010
6
7
4
5
2
3
0
1
110
111
100
101
010
011
000
001
7
6
5
4
3
2
1
0
111
110
101
100
011
010
001
000
latency
The beginning data-output cycle of a read burst can be programmed to occur two or three CLK cycles after the
READ command (see Figure 2 on how to set the mode register.) This feature allows adjustment of the ’664xx4
to operate in accordance with the system’s capability to latch the data output from the ’664xx4. The delay
between the READ command and the beginning of the output burst is known as CAS latency (also known as
read latency). After the initial output cycle begins, the data burst occurs at the CLK frequency without any
intervening gaps. Use of minimum CAS latencies is restricted, based on the particular maximum frequency
rating of the ’664xx4. Once the mode register has been set (see the section on setting the mode register),
subsequent changes to the CAS latency are prohibited.
There is no latency for data-in cycles (write latency). The first data-in cycle of a write burst is entered at the same
rising edge of CLK as the WRT command. The write latency is fixed and is not determined by the mode-register
contents.
four-bank operation
The ’664xx4 contains four independent banks that can be accessed individually or in an interleaved fashion.
Each bank must be activated with a row address before it can be accessed. Each bank then must be deactivated
before it can be activated again with a new row address. The bank-activate/row-address-entry command
(ACTV) is entered by holding RAS low, CAS high, W high, and A12–A13 valid on the rising edge of CLK. A bank
can be deactivated either automatically during a READ (READ-P) or a WRT (WRT-P) command, or by using
the bank-deactivate (DEAC) command. All banks can be deactivated at once by using the DCAB command (see
Table 1 for a description of the bank-deactivation, and Figure 25 and Figure 26 for examples of the operation).
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| TMS664814 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
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