參數(shù)資料
型號(hào)： TMS32C6411AZLZ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： FIXED POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 89/119頁
文件大小： 1742K
代理商： TMS32C6411AZLZ
SPRS196H MARCH 2002 REVISED JULY 2004
89
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles
(see Figure 35)
NO.
300
UNIT
MIN
MAX
3
th(HOLDAL-HOLDL)
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns.
Hold time, HOLD low after HOLDA low
E
ns
switching characteristics over recommended operating conditions for the HOLD/HOLDA
cycles
§
(see Figure 35)
NO.
PARAMETER
300
UNIT
MIN
MAX
1
td(HOLDL-EMHZ)
td(EMHZ-HOLDAL)
td(HOLDH-EMLZ)
td(EMLZ-HOLDAH)
td(HOLDL-EKOHZ)
td(HOLDH-EKOLZ)
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns.
EMIF Bus consists of: CE[3:0], BE[3:0], ED[31:0], EA[22:3], ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE
,
SDCKE,
SOE3, and PDT.
§The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35.
All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
Delay time, HOLD low to EMIF Bus high impedance
2E
ns
2
Delay time, EMIF Bus high impedance to HOLDA low
0
2E
ns
4
Delay time, HOLD high to EMIF Bus low impedance
2E
7E
ns
5
Delay time, EMIF Bus low impedance to HOLDA high
0
2E
ns
6
Delay time, HOLD low to ECLKOUTx high impedance
2E
ns
7
Delay time, HOLD high to ECLKOUTx low impedance
2E
7E
ns
HOLD
HOLDA
EMIF Bus
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
C6411
C6411
1
3
2
5
4
ECLKOUTx
(EKxHZ = 0)
ECLKOUTx
(EKxHZ = 1)
6
7
EMIF Bus consists of: CE[3:0], BE[3:0], ED[31:0], EA[22:3], ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE, SDCKE,
SOE3, and PDT.
The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35.
Figure 35. HOLD/HOLDA Timing
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