參數(shù)資料
型號(hào): TMS320LC546
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors(20/25ns指令周期, 高性能,大并行度,特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的DSP)
中文描述: 數(shù)字信號(hào)處理器(20/25ns指令周期,高性能,大并行度,特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的數(shù)字信號(hào)處理器)
文件頁(yè)數(shù): 4/107頁(yè)
文件大?。?/td> 2149K
代理商: TMS320LC546
TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
17-
×
17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Data Bus With a Bus Holder Feature
Address Bus With a Bus Holder Feature
(’LC548 Only)
Extended Addressing Mode for 8M
×
16-Bit
Maximum Addressable External Program
Space (’LC548)
192K
×
16-Bit Maximum Addressable
Memory Space (64K Words Program,
64K Words Data, and 64K Words I/O)
On-Chip ROM with Some Configurable to
Program/Data Memory
Dual-Access On-Chip RAM
Single-Instruction Repeat and
Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for Better
Program and Data Management
Instructions With a 32-Bit Long Word
Operand
Instructions With Two- or Three-Operand
Reads
Arithmetic Instructions With Parallel Store
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable Bank
Switching
– On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
– Full-Duplex Serial Port to Support 8- or
16-Bit Transfers (’C541, ’LC541, ’LC545,
and ’LC546 Only)
– Time-Division Multiplexed (TDM) Serial
Port (’C542, ’LC542, ’LC543, and ’LC548
Only)
– Buffered Serial Port (BSP) (’C542,
’LC542, ’LC543, ’LC545, ’LC546, and
’LC548 Only)
– 8-Bit Parallel Host Port Interface (HPI)
(’C542, ’LC542, ’LC545, and ’LC548 Only)
– One 16-Bit Timer
– External-Input/Output (XIO) Off Control
to Disable the External Data Bus,
Address Bus and Control Signals
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
CLKOUT Off Control to Disable the
CLKOUT
On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1
(JTAG) Boundary Scan
Logic
25-ns Single-Cycle Fixed-Point Instruction
Execution Time [40 Million Instructions per
Second (MIPS)] for 5-V Power Supply
(’C541 and ’C542 Only)
20-ns and 25-ns Single-Cycle Fixed-Point
Instruction Execution Time (50 MIPS and
40 MIPS) for 3-V Power Supply (’LC54x)
15-ns Single-Cycle Fixed-Point Instruction
Execution Time (66 MIPS) for 3-V Power
Supply (’LC54xA, ’LC548)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
A
Copyright
1997, Texas Instruments Incorporated
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
ADVANCE INFORMATION concerns new products in the sampling or
specifications are subject to change without notice.
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