參數(shù)資料
型號: TMS320LC546
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors(20/25ns指令周期, 高性能,大并行度,特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的DSP)
中文描述: 數(shù)字信號處理器(20/25ns指令周期,高性能,大并行度,特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的數(shù)字信號處理器)
文件頁數(shù): 18/107頁
文件大小: 2149K
代理商: TMS320LC546
TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
’C54x/’LC54x Signal Descriptions (Continued)
TERMINAL
NAME
DESCRIPTION
TYPE
SERIAL PORT 0 AND SERIAL PORT 1 SIGNALS (CONTINUED)
FSX0
FSX1
I/O/Z
Frame synchronization pulse for transmit input/output. The falling edge of the FSX pulse initiates the data trans-
mit process, beginning the clocking of the XSR. Following reset, the default operating condition of FSX is an input.
FSX0 and FSX1 can be selected by software to be an output when TXM in the serial control register is set to 1.
This pin goes into the high-impedance state when EMU1/OFF is low.
TDM SERIAL-PORT SIGNAL
TCLKR
I
TDM receive clock input
TDR
I
TDM serial data-receive input
TFSR/TADD
I/O
TDM receive frame synchronization or TDM address
TCLKX
I/O/Z
TDM transmit clock
TDX
O/Z
TDM serial data-transmit output
TFSX/TFRM
I/O/Z
TDM transmit frame synchronization
MISCELLANEOUS PIN
NC
No connection
HOST PORT INTERFACE SIGNALS
HD0–HD7
I/O/Z
Parallel bidirectional data bus. HD0–HD7 are placed in the high-impedance state when not outputting data. The
signals go into the high-impedance state when EMU1/OFF is low.
HCNTL0
HCNTL1
I
Control inputs
HBIL
I
Byte-identification input
HCS
I
Chip-select input
HDS1
HDS2
I
Data strobe inputs
HAS
I
Address strobe input
HR/W
I
Read/write input
HRDY
O/Z
Ready output. This signal goes into the high-impedance state when EMU1/OFF is low.
Interrupt output. When the DSP is in reset, this signal is driven high
.
The signal goes into the high-impedance
state when EMU1/OFF is low.
HINT
O/Z
HPIENA
I
HPI module select input. This signal must be tied to a logic 1 state to have HPI selected. If this input is left open
or connected to ground, the HPI module will not be selected, internal pullup for the HPI input pins are enabled,
and the HPI data bus has keepers set. This input is provided with an internal pull-down resistor which is active
only when RS is low. HPIENA is sampled when RS goes high and ignored until RS goes low again. Refer to the
Electrical Characteristics section for the input current requirements for this pin.
SUPPLY PINS
CVDD
DVDD
VSS
Supply
+VDD. CVDD is the dedicated power supply for the core CPU.
+VDD. DVDD is the dedicated power supply for I/O pins.
Ground. VSS is the dedicated power ground for the device.
IEEE1149.1 TEST PINS
Supply
Supply
TCK
I
IEEE standard 1149.1 test clock. This is normally a free-running clock signal with a 50% duty cycle. The changes
on the test-access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register,
or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the
falling edge of TCK.
TDI
I
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
I = Input, O = Output, Z = High impedance
A
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