參數(shù)資料
型號(hào)： TMS320F2809_07
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 114/140頁
文件大小： 1108K
代理商： TMS320F2809_07
www.ti.com
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J–OCTOBER 2003–REVISED SEPTEMBER 2007
Table 6-25. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
MIN
TYP
150
MAX
310
UNIT
ps
Micro Edge Positioning (MEP) step size
(1)
(1)
Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase
with low voltage and high temperature and decrease with voltage and cold temperature.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
Table 6-26
shows the eCAP timing requirement and
Table 6-27
shows the eCAP switching characteristics.
Table 6-26. Enhanced Capture (eCAP) Timing Requirement
(1)
TEST CONDITIONS
Asynchronous
Synchronous
With input qualifier
MIN
MAX
UNIT
cycles
cycles
cycles
t
w(CAP)
Capture input pulse width
2t
c(SCO)
2t
c(SCO)
1t
c(SCO)
+ t
w(IQSW)
(1)
For an explanation of the input qualifier parameters, see
Table 6-15
.
Table 6-27. eCAP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
t
w(APWM)
Pulse duration, APWMx output high/low
Table 6-28
shows the eQEP timing requirement and
Table 6-29
shows the eQEP switching
characteristics.
Table 6-28. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
(1)
TEST CONDITIONS
Asynchronous/synchronous
With input qualifier
Asynchronous/synchronous
With input qualifier
Asynchronous/synchronous
With input qualifier
Asynchronous/synchronous
With input qualifier
Asynchronous/synchronous
With input qualifier
MIN
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
t
w(QEPP)
QEP input period
2t
c(SCO)
2(1t
c(SCO)
+ t
w(IQSW)
)
t
w(INDEXH)
QEP Index Input High time
2t
c(SCO)
2t
c(SCO)
+t
w(IQSW)
t
w(INDEXL)
QEP Index Input Low time
2t
c(SCO)
2t
c(SCO)
+ t
w(IQSW)
t
w(STROBH)
QEP Strobe High time
2t
c(SCO)
2t
c(SCO)
+ t
w(IQSW)
t
w(STROBL)
QEP Strobe Input Low time
2t
c(SCO)
2t
c(SCO)
+t
w(IQSW)
(1)
For an explanation of the input qualifier parameters, see
Table 6-15
.
Table 6-29. eQEP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
cycles
cycles
t
d(CNTR)xin
t
d(PCS-OUT)QEP
Delay time, external clock to counter increment
Delay time, QEP input edge to position compare sync output
4t
c(SCO)
6t
c(SCO)
Table 6-30. External ADC Start-of-Conversion Switching Characteristics
PARAMETER
Pulse duration, ADCSOCAO low
MIN
MAX
UNIT
cycles
t
w(ADCSOCAL)
32t
c(HCO)
Electrical Specifications
114
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