參數(shù)資料
型號: TMS320F28044ZGMA
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processor
中文描述: 數(shù)字信號處理器
文件頁數(shù): 92/107頁
文件大?。?/td> 784K
代理商: TMS320F28044ZGMA
www.ti.com
9
4
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
8
5
3
2
1
SPISTE
(A)
TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
A.
In the master mode, SPISTE goes active 0.5t
c(SPC)
(minimum) before valid SPI clock edge. On the trailing end of the
word, the SPISTE will go inactive 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit, except that SPISTE
stays active between back-to-back transmit words in both FIFO and nonFIFO modes.
Figure 6-16. SPI Master Mode External Timing (Clock Phase = 0)
Electrical Specifications
92
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