參數(shù)資料
型號： TMS320F28044PZQ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processor
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 13/105頁
文件大?。?/td> 768K
代理商： TMS320F28044PZQ
www.ti.com
A
2.2
Signal Descriptions
TMS320F28044
Digital Signal Processor
SPRS357A–AUGUST 2006–REVISED OCTOBER 2006
Table 2-2
describes the signals on the 28044 device. All digital inputs are TTL-compatible. All outputs are
3.3 V with CMOS levels. Inputs are not 5-V tolerant.
Table 2-2. Signal Descriptions
PIN NO.
GGM/
ZGM
BALL #
NAME
DESCRIPTION
(1)
PZ
PIN #
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active
high test pin and must be maintained low at all times during normal device operation. In a low-noise
environment, TRST may be left floating. In other instances, an external pulldown resistor is
highly
recommended
. The value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-k
resistor generally offers adequate protection. Since this is
application-specific, it is recommended that each target board be validated for proper operation of
the debugger and the application. (I,
↓
)
JTAG test clock with internal pullup (I,
↑
)
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (I,
↑
)
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
or data) on a rising edge of TCK. (I,
↑
)
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)
are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
(I/O/Z, 8 mA drive
↑
)
NOTE:
An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-k
to 4.7-k
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
(I/O/Z, 8 mA drive
↑
)
NOTE:
An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-k
to 4.7-k
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
FLASH
3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. On the ROM
parts (C280x), this pin should be connected to V
DDIO
.
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
CLOCK
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0
(XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal
can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is not
placed in high-impedance state during a reset. (O/Z, 8 mA drive).
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case,
the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.8-V oscillator is
used to feed clock to X1 pin), this pin must be tied to GND. (I)
TRST
84
A6
TCK
75
A10
TMS
74
B10
TDI
73
C9
TDO
76
B9
EMU0
80
A8
EMU1
81
B7
V
DD3VFL
96
C4
TEST1
TEST2
97
98
A3
B3
XCLKOUT
66
E8
XCLKIN
90
B5
(1)
I = Input, O = Output, Z = High impedance, OD = Open drain,
↑
= Pullup,
↓
= Pulldown
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Introduction
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