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TMS320F28044
Digital Signal Processor
SPRS357A–AUGUST 2006–REVISED OCTOBER 2006
List of Tables
2-1
Hardware Features
...............................................................................................................
10
Signal Descriptions
...............................................................................................................
13
Addresses of Flash Sectors
.....................................................................................................
21
Wait-states
.........................................................................................................................
22
Boot Mode Selection
..............................................................................................................
24
Peripheral Frame 0 Registers
...................................................................................................
28
Peripheral Frame 1 Registers
...................................................................................................
29
Peripheral Frame 2 Registers
...................................................................................................
29
Device Emulation Registers
.....................................................................................................
29
PIE Peripheral Interrupts
.........................................................................................................
31
PIE Configuration and Control Registers
......................................................................................
32
External Interrupt Registers
......................................................................................................
32
PLL, Clocking, Watchdog, and Low-Power Mode Registers
................................................................
34
PLLCR Register Bit Definitions
..................................................................................................
36
Possible PLL Configuration Modes
.............................................................................................
37
Low-Power Modes
................................................................................................................
39
CPU-Timers 0, 1, 2 Configuration and Control Registers
...................................................................
41
ePWM1-4 Control and Status Registers
.......................................................................................
43
ePWM5-8 Control and Status Registers
.......................................................................................
44
ePWM9-12 Control and Status Registers
......................................................................................
45
ePWM13-16 Control and Status Registers
....................................................................................
46
ADC Registers
.....................................................................................................................
52
SCI-A Registers
...................................................................................................................
54
SPI-A Registers
...................................................................................................................
57
I
2
C-A Registers
....................................................................................................................
60
GPIO Registers
...................................................................................................................
62
F28044 GPIO MUX Table
........................................................................................................
63
TMS320F28044 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
.............................
71
Typical Current Consumption by Various Peripherals (at 100 MHz)
.......................................................
72
TMS320x280x Clock Table and Nomenclature
...............................................................................
75
Input Clock Frequency
...........................................................................................................
76
XCLKIN Timing Requirements - PLL Enabled
................................................................................
76
XCLKIN Timing Requirements - PLL Disabled
................................................................................
76
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
.........................................................
76
Power Management and Supervisory Circuit Solutions
......................................................................
77
Reset (XRS) Timing Requirements
............................................................................................
79
General-Purpose Output Switching Characteristics
..........................................................................
80
General-Purpose Input Timing Requirements
.................................................................................
81
IDLE Mode Timing Requirements
...............................................................................................
83
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
List of Tables
6
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