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Contents
TMS320F28044
Digital Signal Processor
SPRS357A–AUGUST 2006–REVISED OCTOBER 2006
1
F28044 Digital Signal Processor
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9
1.1
Features
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9
Introduction
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10
2.1
Pin Assignments
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10
2.2
Signal Descriptions
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13
Functional Overview
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19
3.1
Memory Map
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20
3.2
Brief Descriptions
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22
3.2.1
C28x CPU
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22
3.2.2
Memory Bus (Harvard Bus Architecture)
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22
3.2.3
Peripheral Bus
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23
3.2.4
Real-Time JTAG and Analysis
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23
3.2.5
Flash
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23
3.2.6
M0, M1 SARAMs
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23
3.2.7
L0, L1 SARAMs
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23
3.2.8
Boot ROM
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24
3.2.9
Security
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25
3.2.10
Peripheral Interrupt Expansion (PIE) Block
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26
3.2.11
External Interrupts (XINT1, XINT2, XNMI)
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26
3.2.12
Oscillator and PLL
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26
3.2.13
Watchdog
........................................................................................................
26
3.2.14
Peripheral Clocking
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26
3.2.15
Low-Power Modes
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26
3.2.16
Peripheral Frames 0, 1, 2 (PFn)
..............................................................................
27
3.2.17
General-Purpose Input/Output (GPIO) Multiplexer
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27
3.2.18
32-Bit CPU-Timers (0, 1, 2)
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27
3.2.19
Control Peripherals
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27
3.2.20
Serial Port Peripherals
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28
3.3
Register Map
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28
3.4
Device Emulation Registers
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29
3.5
Interrupts
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30
3.5.1
External Interrupts
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32
3.6
System Control
.............................................................................................................
33
3.6.1
OSC and PLL Block
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35
3.6.2
Watchdog Block
.................................................................................................
37
3.7
Low-Power Modes Block
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39
Peripherals
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40
4.1
32-Bit CPU-Timers 0/1/2
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40
4.2
Enhanced PWM Modules (ePWM1-16)
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42
4.3
Hi-Resolution PWM (HRPWM)
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47
4.4
Enhanced Analog-to-Digital Converter (ADC) Module
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48
4.5
Serial Communications Interface (SCI) Module (SCI-A)
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53
4.6
Serial Peripheral Interface (SPI) Module (SPI-A)
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56
4.7
Inter-Integrated Circuit (I
2
C)
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59
4.8
GPIO MUX
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61
Device Support
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65
5.1
Device and Development Support Tool Nomenclature
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65
5.2
Documentation Support
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67
Electrical Specifications
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69
6.1
Absolute Maximum Ratings
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69
2
3
4
5
6
Contents
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